Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Design partition: Error (18999): Placement cannot find a legal solution.

Yogesh
Novice
1,117 Views

I have designed a design partition file and generated .qxp file . After importing that file and declaring the file along with top level codes . I am using post fit - netlist type . preservation level - placement and routing .

After starting compilation , fitter fails giving below error :

Error (18999): Placement cannot find a legal solution.

Error (170079): Cannot place node <name>of type MLAB cell.

 

How to solve this error ? Please reply as soon as possible.

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5 Replies
AEsqu
Novice
1,098 Views

Did you try to disable the logic lock region assignments?

 

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Yogesh
Novice
1,092 Views

Yes, If I disable logic lock regions . Fitter will pass without giving errors. 

But , frequency achieved will drop drastically.

I want to retain maximum frequency which I had achieved while creating logic lock region .I have explained the same below:-

Say I have 3 modules:

1) Top module 

 2) sub-module A-(achieved freq 150Mhz when compiled separately)

3) sub-module B-(achieved freq 200 Mhz when compiled separately)

After I instantiate sub-modules A and B in top module , I am getting 80Mhz and 110 Mhz from both respectively. 

So , I thought if I retain the same fitter placement of module B (applying logic lock and design partitioning) I can get same frequency i.e, around 200 Mhz on the Top module .

Please Note that: Fitter used to behave unusally while merging 624 9x9 multipliers into 208 DSPs (cyclone V device) and used to fail sometimes. So Design partiton/ logic lock is very important for me .

But here ,if I try to retain the routing and placement  netlist , I get the above error .

If I remove logic lock fitter will pass but timing falls drastically. 

So, please suggest me how to solve this issue.

 

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Yogesh
Novice
1,061 Views

Hi,

if I remove logic lock, fitter will fail sometimes because of high routing congestion. How should I go about solving the problem?

 

regards,

Yogesh

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RichardTanSY_Intel
998 Views

Sorry for idling for some time, do you still need help on this?


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AEsqu
Novice
992 Views

Hi,

It solved by itlsef but I don't remember how.

Could have been due to quartus settings changed or new quatus version.

This can be closed. Have a nice day.

 

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