11-17-2017 08:23 AM
Hallo,I used Quartus 16.1.203 to compile a design where I used a FIFO IP which is, I assume is synthesised/built as a RAM. The compilation is successful. But in the summary I do not see the amount of RAM used which is empty, and can not locate it in the Chip Planner either. Though the RTL Viewer shows the block and the connections. What could be the reason? attached you find a image of the resource utilization.(where capdev_rx_infifo is empty) Thanks, Alex.
- FPGA Design Tools
11-17-2017 09:09 AM
--- Quote Start --- I assume is synthesised/built as a RAM --- Quote End --- I assume your assumption is questionable... When you configure your IP you can, depending on device family and IP, chose whether to use RAM (including type if appropriate) or logic or let Quartus decide. What other resource utilisation do you see? Has Quartus simply constructed it from logic? Cheers, Alex
11-20-2017 11:24 AM
Then I assume Quartus has decided your FIFO is unnecessary to implement your design and has stripped it out. Have you connected it up correctly?Cheers, Alex