Hi,I would like to ask if default signal assignments have any meaning in clocked processes. In non-clocked it is an easy way to avoid latches, but in clocked processes can they be useful without adding extra circuit? will altera synthesizer behave differently between a) default signal assignment and b) using if then else for all signals ? I talk always about clocked processes Thanks
It should give the same logic.Its quite normal to provide a default value in a state machine for example, where the change in value is only assigned in specific states.