Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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default signal assignments

Altera_Forum
Honored Contributor II
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Hi, 

 

I would like to ask if default signal assignments have any meaning in clocked processes. In non-clocked it is an easy way to avoid latches, but in clocked processes can they be useful without adding extra circuit? 

will altera synthesizer behave differently between a) default signal assignment and b) using if then else for all signals ? I talk always about clocked processes 

 

Thanks
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Altera_Forum
Honored Contributor II
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It should give the same logic.  

Its quite normal to provide a default value in a state machine for example, where the change in value is only assigned in specific states.
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