After studying "TimeQuest Timing Analyzer Quick Start Tutorial" (Document Version: 1.1, Dec. 2009 ), I found that timing constraints seem not applicable to the analysis & synthesis tool quartus_map. Timing constraints are only considered by place & rout tool quartus_fit.
Am I correct?
I'm curious about this because timing constraints is necessary for ASIC synthesis, as they instruct synthesizer how to generate a netlist that meets user's timing requirement. Does quartus_map really NOT use timing constraints??
Hi Khai Chein,
Thanks for your prompt reply and confirmation.
Then, is there any document/tutorial that describes how to instruct Quartus II's synthesis tool to use timing constraints while it is doing synthesis?
A document from 2009 is not going to describe this since synthesis support for .sdc was added later.
You don't need to do anything for this to work. It is just part of the compiler now. As long as you've added a .sdc file to the project (Assignments menu -> Settings -> Timing Analyzer), you're good to go.