Re: Error (10759): Verilog HDL error... -> is Verilog-2001 not supported?

Altera_Forum · ‎01-18-2017

Hi All,

I'm receiving the "Error (10759): Verilog HDL error at rly.v(18): object rl_sck declared in a list of port declarations cannot be re-declared within the module body" on the following code:


module rly 
 (//** System
  input           clk,
  input           rstn,
  output          rl_sck,
);
//////////////////////////////////////////////////////////////////////
//* DECLARATIONS
//////////////////////////////////////////////////////////////////////
reg            rl_sck;
endmodule

why this is an error? This is actually a legal verilog-2001 syntax. This module is defined as SystemVerilog HDL file in Quartus-II.

Thank you!

Altera_Forum · ‎01-18-2017

Remove the comma after rl_sck in the port list.

Cheers,

Alex

Altera_Forum · ‎01-18-2017

SystemVerilog is SystemVerilog-2005, and the LRM 19.8 says:

--- Quote Start ---

For the first port, if neither a type nor a direction is specified, then it shall be assumed to be a member of a

port list, and any port direction or type declarations must be declared after the port list. This is compatible

with the Verilog-1995 syntax. If the first port kind or data type is specified, but no direction is specified,

then the port direction shall default to inout. If the first port direction is specified, but no port kind or data

type is specified, then the port shall default to a net of net type wire. This default net type can be changed

using the ‘default_nettype compiler directive, as in Verilog.

--- Quote End ---

So because you declared rl_sck as output, it defaults to wire type and cannot be re-declared

So yes - it is legal 2001 syntax, but not 2005 (which systemverilog is)

Altera_Forum · ‎01-18-2017

Thanks! It's really that SV-2005 is no so compatible with V-2001!

Altera_Forum · ‎01-18-2017

--- Quote Start ---

Thanks! It's really that SV-2005 is no so compatible with V-2001!

--- Quote End ---

Yes - SV is not fully backward compatible.