Error (10759) when compile boardtest.cl kernel

[Altera_Forum]

when i run to compile boardtest.cl kernel, have the bellow error : error (10759) the verilog hdl error at boardtest_system.v :object kclk_finish declared in a list of port decralation cannot be redeclared within the module body file: e:/intelFPGA/17.1/hld/board/terasic/de1soc/example/boardtest/bin/boardtest/system/systhesis/submodule/boardtest_system.v line 488 

 did that file generate automatically?why still this error

[Altera_Forum]

Please attach the "quartus_sh_compile.log" file.

[Altera_Forum]

the quartus_sh_compile file attached ,please check...

[Altera_Forum]

--- Quote Start ---  Info (125068): Revision "top" was previously opened in Quartus II software version 16.0.2. Created Quartus Prime Default Settings File E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/top_assignment_defaults.qdf, which contains the default assignment setting information from Quartus II software version 16.0.2.  --- Quote End ---    It seems the BSP you are using is not compatible with your version of Quartus. Check your board manufacturer's instructions as to which version of Quartus you should be using.

[Altera_Forum]

yes，i'm using quartus 17.1version while the BSP version of de1soc board is 16.0. but the de1-soc opencl user manual file don't write that bsp only install under quartus v16.0,so i'm not sure that error was caused by different version...

[Altera_Forum]

You can install Quartus 16.0.2 alongside with the version you have now and try to see if it works. If it still didn't, I recommend contacting Terasic's support.