Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Error(16169): Instance "" has an ambiguous entity binding


I converted my first working quartus design from Quartus prime 18.0 to Quartus pro 18.0. The pro tool prompted me some auto changes (directory and IP upgrade) to which I clicked OK. The design however failed compile and synthesis step giving the following cryptic errors:


Info: Version 18.0.0 Build 219 04/25/2018 SJ Pro Edition

Info: Processing started: Tue Oct 30 00:35:58 2018

Info: Command: quartus_syn --read_settings_files=on --write_settings_files=off my_first_quartus_design -c my_first_quartus_design

Info: qis_default_flow_script.tcl version: #1

Info: Initializing Synthesis...

Info: Project = "my_first_quartus_design"

Info: Revision = "my_first_quartus_design"

Info: Analyzing source files

Info: Elaborating from top-level entity "my_first_quartus_design"

Error(16169): Instance "" has an ambiguous entity binding

              Error(16170): Could be "work.my_first_quartus_design"

              Error(16170): Could be "altera_work.my_first_quartus_design"

Error(16368): Top-level design entity "my_first_quartus_design" is undefined

Error(16186): Can't elaborate top-level user hierarchy

Error: Flow failed: 

Error: Quartus Prime Synthesis was unsuccessful. 6 errors, 0 warnings

              Error: Peak virtual memory: 1036 megabytes

              Error: Processing ended: Tue Oct 30 00:36:17 2018

              Error: Elapsed time: 00:00:19

              Error: Total CPU time (on all processors): 00:00:10

Error(293001): Quartus Prime Full Compilation was unsuccessful. 8 errors, 0 warnings


I have marked my_first_quartus_design.bdf as the top level entity in files menu.


BTW, why compute stats at the end are treated as errors?



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4 Replies

Hi Suhas,

From which Quartus prime 18.0 edition are you converting to Quartus pro 18.0 ?

Do you come across any error while IP upgradation? provide screenshot.


Best Regards

Vikas Jathar 

(This message was posted on behalf of Intel Corporation)


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Hi Vicky,


I'm converting from the following Quartus Prime version. That is the only one I can download.

# Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition


Hi Abe,

 I looked up the KDB link which talks about Quartus-II tool and provides the following explanation. I am not sure how much of this applies to Quartus Prime or Pro editions.


"These errors indicate a conflict in files generated for multiple IP cores. Each IP core should be compiled into its own design library as indicated in its Quartus II IP (.qip) file. If you see these errors, verify that your Quartus II Settings File (.qsf) file only calls out the .qip files for each IP core. You should not include any of the files listed in the .qip file directly in the .qsf."


I see the following line in .qsf file. I also have pll directory where there is .qip file. Not sure if this causes conflict.

set_global_assignment -name QSYS_FILE pll.qsys


I was expecting the tool to clean up everything as I didn't generate the .qsf file.







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Honored Contributor III

That KDB article linked above is not the same as what you are seeing. The issue you are having has to do with the stricter library use in Pro edition synthesis vs. how it was handled in Standard edition. See the "Upgrade Non-Compliant Design RTL" section of the Pro Getting Started User Guide:

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