Error reading file

Altera_Forum · ‎04-03-2011

Hi I'm trying to read a text file which is basically many lines of 1s and 0s, e.g.

1

0

1

0

At the moment if I include the file I get the following error message when I try to compile:

Error (10170): Verilog HDL syntax error at data_file.txt(1) near text "1"; expecting an identifier, or "endmodule", or a parallel statement

and the cursor is on the first line of the added file. There are many bits in this file so I need to change the verilog method of reading I suppose, but I don't know how.

The syntax I'm trying to use is:

// include file (outside module description)

`include "C:\*path*\data_file.txt"

integer fileID;

initial begin

fileID = $fopen("data_file.txt", "r");

end

I have also tried to read it without the include line with:

fileID = $fopen("*path*data_file.txt", "r");

but then I get error message:

Error (10174): Verilog HDL Unsupported Feature error at datafile9.v(21): system function "$fopen" is not supported for synthesis

Any help would be very much appreciated.

Altera_Forum · ‎04-03-2011

what "include" statement means that replace the statement from the file.

what you did is compiling just numbers in VerilogHDL.

that doesn't make sense.

in term of $fopen case.

actually verilog-HDL does support $fopen.

but QuartusII does not support some case of Verilog rules.

how about that prepare file like that

//-----------------------------------------------

`define MYNUMBER 32'h00FF00FF00FFFFF

//-----------------------------------------------

and use the definition in your code.

//-----------------------------------------------

fileID = `MYNUMBER;

//-----------------------------------------------

does it help for you?

Altera_Forum · ‎06-24-2016

Hi, I am having the same issue with $fopen.

I am trying to read in an .rbf file and use the following snippet of code:

integer file;

file = $fopen("helper.rbf", "r");

and receive this error:

Error (10174): Verilog HDL Unsupported Feature error at testbench.v(40): system function "$fopen" is not supported for synthesis

I followed what you suggested by storing the file ID to a variable, but I also need to read in the file. Here is part of my code

integer char;

integer file = 32'h3C2718;

char = $fgetc(file);

I receive this error:

Error (10174): Verilog HDL Unsupported Feature error at testbench.v(40): system function "$fgetc" is not supported for synthesis

Note-I am doing simulation only. I compile using Processing->Start->Start Analysis & Elaboration

I am using Quartus II v16.0 on linux

Is there another method where I can read and write to a file?

Thanks

Altera_Forum · ‎06-24-2016

I found what I was doing wrong, I need to use ModelSim to compile my testbench instead of quartus.

Altera_Forum · ‎06-26-2016

You may also use synthesis translate_off/on synthesis directive to tell quartus excude part of you source file from sythesis. Sometimes it's very usefull. http://quartushelp.altera.com/14.0/mergedprojects/hdl/vlog/vlog_file_dir_translate.htm