Errors when trying to create 24 hr clock in Quartus II using VHDL

Altera_Forum · ‎04-30-2016

I am news to VHDL and trying to create a 24 hr clock with hours, minutes and seconds that outputs on the seven segment display but I am getting errors and have been unable to resolve them. Here is the code.


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity clocker is
    port (CLOCK_50: in std_logic;
            printer: in std_logic_vector(15 downto 0);
            enter: in std_logic_vector(3 downto 0);
            out1, out2, 
            out3, out4, 
            out5, out6, 
            out7, out8 : out std_logic_vector(0 to 6));
end clocker;
architecture Behavior of clocker is 
    component ring
    port (dividor, divisor : in std_logic_vector(3 downto 0);
            clock2, reset, inner, outer : in std_logic_vector(3 downto 0);
            p: out std_logic_vector(3 downto 0));
    end component;
    
    component printOut2
        port( digit : in std_logic_vector(3 downto 0);
                print : out std_logic_vector(0 to 6));
    end component;
    
    signal count: std_logic_vector(24 downto 0);
    signal h0, h1, m0, m1, s0, s1: std_logic_vector(3 downto 0);
    signal divh0: std_logic_vector(3 downto 0);
    signal sec0, sec1, min0, min1, hr0, hr1: std_logic;
begin
    process(CLOCK_50)
    begin    
        if (CLOCK_50'event and CLOCK_50 ='1') then 
            count <= count + '1';
        end if;
    end process;
    
    sec0 <= '1' when (count = 0) else '0';
    secs0: ring port map ("0000", "1001", CLOCK_50, enter(3), '0', sec0, s0);
    sec1 <= '1' when (s0 = 9) and (sec0 = '1') else '0';
    secs1: ring port map ("0000", "0101", CLOCK_50, enter(3), '0', sec1, s1);
    
    min0 <= '1' when (s1 = 5) and (sec1 = '1') else '0';
    mins0: ring port map (printer(3 downto 0), "1001", CLOCK_50, enter(3), not enter(0), min0, m0);
    min1 <= '1' when (m0 = 9) and (min0 = '1') else '0';
    mins1 : ring port map(printer(7 downto 4), "0101", CLOCK_50, enter(3), not enter(0), min1, m1);
    
    hr0 <= '1' when (m1 = 5) and (min1 = '1') else '0';
    divh0 <= "0011" when (h1 = 2) else "1001";
    hrs0: ring port map(printer(11 downto 8), divh0, CLOCK_50, enter(3), not enter(0), hr1, h0);
    hr1 <= '1' when (((h1 = 2) and (h0 = 3)) or (h0 = 9)) and (hr0 = '1') else '0';
    hrs1 :ring port map (printer(15 downto 12), "0010", CLOCK_50, enter(3), not enter(0), hr1, h1);
    hrs1: ring port map (printer(15 downto 12), "0010", CLOCK_50, enter(3), not enter(0), hr1, h1);
    
    d7: printOut port map (h1, out8);
    d6: printOut port map (h0, out7);
    d5: printOut port map (m1, out6);
    d4: printOut port map (m0, out5);
    d3: printOut port map (s1, out4);
    d2: printOut port map (s0, out3);
    d1: printOut port map ("1111", out2);
    d0: printOut port map ("1111", out1);
    
end Behavior;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ring is
    port (dividor, divisor : in std std_logic_vector(3 downto 0);
            clock2, reset, inner, outer : in std_logic_vector(3 downto 0);
            p: out std_logic_vector(3 downto 0));
end ring;
architecture Behavior of ring is 
    signal count2: std_logic_vector(3 downto 0);
begin
    process(clock2)
    begin
        if (clock2 = '1' and clock2'event) then 
            if (reset = '0') then
                count2 <= "0000";
            elsif (inner = '1') then 
                count2 <= dividor;
            elsif (outer = '1') then
                if (count2 = divisor) then
                    count2 <= "0000";
                else 
                    count2 <= count + '1';
                end if;
            end if;
        end if;
    end process;
    p <= count2;
end Behavior;
library ieee;
use ieee.std_logic_1164.all;
entity printOut2 is 
        port( digit : in std_logic_vector(3 downto 0);
                print : out std_logic_vector(0 to 6));
end printOut2;
architecture Behavior of printOut2 is 
begin
    process(digit)
    begin 
        case(digit) is
            when "0000" => print <= "0000001";
            when "0001" => print <= "1001111";
            when "0010" => print <= "0010010";
            when "0011" => print <= "0000110";
            when "0100" => print <= "1001100";
            when "0101" => print <= "0100100";
            when "0110" => print <= "1100000";
            when "0111" => print <= "0001111";
            when "1000" => print <= "0000000";
            when "1001" => print <= "0001100";
            when others => print <= "1111111";
        end case;
    end process;
end Behavior;

The errors I get are:

Error (10476): VHDL error at clocker.vhd(42): type of identifier "CLOCK_50" does not agree with its usage as "std_logic_vector" type

Error (10381): VHDL Type Mismatch error at clocker.vhd(42): indexed name returns a value whose type does not match "std_logic_vector", the type of the target expression

Error (10316): VHDL error at clocker.vhd(42): character ''0'' used but not declared for type "std_logic_vector"

Error (10476): VHDL error at clocker.vhd(42): type of identifier "sec0" does not agree with its usage as "std_logic_vector" type

Please tell me where I am going wrong. Thanks!

Altera_Forum · ‎05-01-2016

Your "ring" components only has std_logic_vector ports, but you are trying to connect a single bit clock to a 4 bit vector.

Did you mean to have the clock2 signal as a std_logic_vector?