Failed to create SystemVerilog interface in _hw.tcl in Platform Designer

[chunxi_yu]

Hi,

I am using Cyclone V and Quartus Prime Standard 22.1.2 (which is the latest downloadable version in Intel website).

There is a user component with 2 AXI interfaces and 1 APB interface in Platform Designer. To simplify the connection I want to use SV interface. I found the description in Platform Designer user guide of how to add SV interface into _hw.tcl and corresponde it with a QSYS interface: https://www.intel.com/content/www/us/en/docs/programmable/683364/18-1/declaring-systemverilog-interfaces-in-hw-tcl.html

But when I added the lines in example script Platform Designer reported errors, e.g.

1. "add_fileset_file axi4_io.sv SYSTEM_VERILOG PATH lib/intf/axi4_io.sv SYSTEMVERILOG_INTERFACE"

   1. Error: SYSTEMVERILOG_INTERFACE not allowed for EFileAttribute, must be in {[TOP_LEVEL_FILE, MENTOR_SPECIFIC, CADENCE_SPECIFIC, SYNOPSYS_SPECIFIC, ALDEC_SPECIFIC, COMMON_SYSTEMVERILOG_PACKAGE, CONTAINS_INLINE_CONFIGURATION, IS_CONFIGURATION_PACKAGE]}

   2. And, the description of SYSTEMVERILOG_INTERFACE in "Fileset Kind Properties" is not consistent with the example which treated it as one of "File Kind Properties". I did try adding a fileset with type SYSTEMVERILOG_INTERFACE but it poped out an error saying it is not one of the valid fileset kind properties neither.
   3. 
2. "add_sv_interface axi_bd_if axi4_io"

   • Error: invalid command name "add_sv_interface" while executing "add_sv_interface axi_bd_if axi4_io"

How to use this function correctly?

[sstrell]

Did you try putting quotes around "lib/intf/axi4_io.sv"?  The screenshot you posted has quotes around the path.

[ShengN_Intel]

Hi,

add_sv_interface and add_fileset_file <file_name>.sv SYSTEM_VERILOG PATH ../<file_name>.sv SYSTEMVERILOG_INTERFACE are attributes supported by pro version only check screenshot.

Standard version don't support those attributes check screenshot. Please use other attributes instead. Probably there're some problem with the document, I'll report this to related document team.

Thanks,

Best Regards,

Sheng

[chunxi_yu]

Hi Sheng,

Thank you for the explanation.

Is my understanding correct that Quartus Prime Standard version doesn't support SV interface in Platform Designer component top-level at all?

Thanks,

Chunxi

[ShengN_Intel]

Hi Chunxi,

SV interface in Platform Designer component top-level is supported in Standard version. Just that attributes (SYSTEMVERILOG_INTERFACE) and add_sv_interface are not supported in Standard version.

So you can still use SV interface in Platform Designer component top-level and not need to use that attributes (SYSTEMVERILOG_INTERFACE). Btw, you can go to File -> Export System as hw.tcl Component to auto-generated the hw.tcl of the component.

Thanks,

Best Regards,

Sheng

[chunxi_yu]

Hi Sheng,

I am using a set of RTL files to create a Platform Designer component for it to be connected with HPS in Platform Designer. 

Without using add_sv_interface,  SV_INTERFACE_PORT,  SV_INTERFACE_PARAMETER, SYSTEMVERILOG_INTERFACE attributes in hw.tcl, how to specify systemverilog interface in hw.tcl in Quartus Prime Standard software? Are there any instructions or examples available?

Thanks,

Chunxi

[ShengN_Intel]

Hi Chunxi ,

In component editor, add the <systemverilog_interface>.sv and <systemverilog_top_module>.sv. Then, set attribute of <systemverilog_top_module>.sv to Top-level File and click Analyze Synthesis File will do. Systemverilog interface module will be linked to systemverilog top module automatically. Attached file for your reference.

Thanks,

Best Regards,

Sheng

[chunxi_yu]

Hi Sheng,

I see your attachement. It is an example of SV interface used inside the RTL but not as a top-level port.

Instead of this:

module or_ex( //top-level

    input logic[3:0] a, b,

    output logic[5:0] sum, sum_new,

     input logic clock_sink_clk, reset_sink_reset

);

logic_gate_if lg ();  // import all signals from interface

Is it possible for Platform Designer to extract signals and corresponds them to IP component interface from below code?

module or_ex( //top-level

    logic_gate_if.sink lg;

    output logic[5:0] sum, sum_new,

     input logic clock_sink_clk, reset_sink_reset

);

Or is the "add sv interface" command in Prime pro edition unable to do this either?

Thanks,

Chunxi

[ShengN_Intel · Accepted solution]

Hi Chunxi,

Done testing. Yes, the top-level port feature that you want can be done by Pro version hw.tcl SystemVerilog interface command.

I had checked internally that this feature only be implemented starting from Pro version 17.1. That's why you'll see package require -exact qsys 17.1 in both the Standard and Pro example given https://www.intel.com/content/www/us/en/docs/programmable/683364/18-1/declaring-systemverilog-interfaces-in-hw-tcl.html and https://www.intel.com/content/www/us/en/docs/programmable/683609/22-4/declaring-systemverilog-interfaces-in-hw-tcl.html

If you check the hw.tcl generated by latest Standard version 22.1.2, you'll see it still use this package require -exact qsys 16.1. Means that Standard version not yet supports this feature and document mistake (I'll report this to internal team). Probably this feature will be supported in future Standard release.

So for now, have to stick with traditional method (SV interface used inside the RTL) for Standard version.

Thanks,

Best Regards,

Sheng