Finite State Machine..

[Altera_Forum]

Hello, 

i have problem here.. please help me out.. I'm designing a vending machine that accept only coins( 10 cent, 20 cent, and 50 cent)  A = 10 cent B = 20 cent C = 50 cent  the error still appear after simulation even i edit the coding several times. :(     LIBRARY ieee; USE ieee.std_logic_1164.all;  ENTITY fsm1 is  PORT ( clk, rst : in std_logic;  A, B, C : in std_logic;  Z : out std_logic);  END fsm1;   ARCHITECTURE structural of fsm1 is  TYPE state is ( s0, s1, s2, s3, s4, s5, s6, s7 );  SIGNAL y : state; BEGIN   fsm_transition: PROCESS ( clk, rst)  BEGIN  IF rst = '1' THEN y <= s0;  ELSIF clk'event and clk = '1' THEN   CASE y is  WHEN s0 => IF A = '1' THEN y <= s1;  ELSIF B = '1' THEN y <= s2;  ELSIF C = '1' THEN y <= s5;  ELSE y <= s0;  END IF;    WHEN s1 => IF A = '1' THEN y <= s2;  ELSIF B = '1' THEN y <= s3;  ELSIF C = '1' THEN y <= s6;  ELSE y <= s1;  END IF;    WHEN s2 => IF A = '1' THEN y <= s3;  ELSIF B = '1' THEN y <= s4;  ELSIF C = '1' THEN y <= s7;  ELSE y <= s2;  END IF;    WHEN s3 => IF A = '1' THEN y <= s4;  ELSIF B = '1' THEN y <= s5;  ELSIF C = '1' THEN y <=s7;  ELSE y <= s3;  END IF;    WHEN s4 => IF A = '1' THEN y <= s5;  ELSIF B = '1' THEN y <= s6;  ELSIF C = '1' THEN y <= s7;  ELSE y <= s4;  END IF;    WHEN s5 => IF A = '1' THEN y <= s6;  ELSIF B = '1' THEN y <= s7;  ELSIF C = '1' THEN y <= s7;  ELSE y <= s5;  END IF;    WHEN s6 => IF A = '1' THEN y <= s7;  ELSIF B = '1' THEN y <= s7;  ELSIF C = '1' THEN y <= s7;  ELSE y <= s6;  END IF;    END CASE;  END IF;  END PROCESS fsm_transition;    Z <= '1' WHEN y = s7 ELSE '0';    END structural;

[Altera_Forum]

You didn't tell about the error at all. It's obvious, that the coin counter advances while any input is activated, this wouldn't work in real life of course. Also, a WHEN s7 => 

or WHEN OTHERS => case may be missing.

[Altera_Forum]

Info: Command: quartus_map --read_settings_files=on --write_settings_files=off fsm1 -c fsm1 --generate_functional_sim_netlist 

Warning: Using design file fsm1.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project  Info: Found design unit 1: fsm1-structural  Info: Found entity 1: fsm1 Info: Elaborating entity "fsm1" for the top level hierarchy error (10313): vhdl case statement error at fsm1.vhd(19): case statement choices must cover all possible values of expression error: can't elaborate top-level user hierarchy error: quartus ii functional simulation netlist generation was unsuccessful. 2 errors, 1 warning  Info: Allocated 167 megabytes of memory during processing  Error: Processing ended: Mon May 05 09:35:49 2008  Error: Elapsed time: 00:00:02

[Altera_Forum]

tQ.. 

i got it.. :D

[Altera_Forum]

My requirement is that my computer program wants to use the information presented by Finite State Machine. For Example what are the states, actions, events and next states. How information of Finite State Machine can be presented before giving it as input to computer program? 

   My program will work as :     Read state and then according to events and actions determine next state. In short I want to implement State Transition Table. I need help which data structure should be used?     Kindly Help me.     Thanks      Regards  Asif Iqbal