Forcing signal for Analyze & Compile at partition boundary

[Altera_Forum]

Does anyone know if it is possible to 'force' a signal to 0 on a lower level design partition boundary for synthesis? 

 The normal way would be to just change the RTL code, possibly with an `ifdef, but this is in external IP that I've been asked not to touch!  More specifically, the partitioned section has an input 'gscanenable' which ends up xnor'd with a clock and used on a couple of registers. But even though gscanenable is tied to 1'b0 at the top level above this partition the optimizer can't see that the signal is always 0 and adds the xnor resulting in hold time errors. (It is otherwise fine as the clock is otherwise undisturbed.)  It would be extremely useful to have a line in the *.qsf file that forces the node to 0.

[Altera_Forum]

Add a level of hierarchy that just instantiates the IP, passes all signals through as normal, but puts '0' in that pin. (An assignment would be easier, but that's the recommended way)

[Altera_Forum]

Hi Rysc, 

Thanks for the speedy reply! Yes, this is what I'm doing above the top level partition. (Similar to the solution of inserting a dummy PLL to get the clocking right shown in the Quartus manual.)  Unfortunately as this is at a lower level of the design (the FPU) and I would have to insert this passthrough module as a sort of 'shim' between the instantiating and sub-partition IP. It would certainly work, but I'd still end up changing the code (if only the instantiation).  As I think that code modification is inevitable I will probably do: `if FPGA `define CPU_SCANENABLE 1'b0 `else `define CPU_SCANENABLE scanenable `endifin the header file and substitute scanenable in the RTL for `cpu_scanenable   If there is a 'new feature' list for Quartus, this would be a useful addition as I know I've bumped into similar issues before (on a competing synthesis tool!)  Regards, ++Simon