Generate Case Instantiation

[Altera_Forum]

Hi, 

 I would like to instantiate a parameterized sub-module "test1" based on an input value SW[6:0]. So I implement a generate case structure as follows:  always @(*) begin  generate  case (SW[6:0])  7'b0000000: begin  test1 t1(.a(SW[6:0]), .b(LEDR[17:6]));  defparam t1.NUM_PULSE = 1;   defparam t1.SAMPLES_PER_CYCLE = 8;  end  7'b0000001: begin  test1 t1(.a(SW[6:0]), .b(LEDR[17:6]));  defparam t1.NUM_PULSE = 1;  defparam t1.SAMPLES_PER_CYCLE = 16;   end  default: begin  test1 t1(.a(SW[6:0]), .b(LEDR[17:6]));  defparam t1.NUM_PULSE = 1;   defparam t1.SAMPLES_PER_CYCLE = 8;  end  endcase  endgenerate end  But the Altera gives me the following errors:  Error (10170): Verilog HDL syntax error at Correlation.v(74) near text "generate"; expecting "end" Error (10170): Verilog HDL syntax error at Correlation.v(77) near text "("; expecting ";" Error (10170): Verilog HDL syntax error at Correlation.v(79) near text "defparam"; expecting "end" Error (10170): Verilog HDL syntax error at Correlation.v(82) near text "("; expecting ";" Error (10170): Verilog HDL syntax error at Correlation.v(84) near text "defparam"; expecting "end" Error (10170): Verilog HDL syntax error at Correlation.v(87) near text "("; expecting ";" Error (10170): Verilog HDL syntax error at Correlation.v(89) near text "defparam"; expecting "end" Error (10170): Verilog HDL syntax error at Correlation.v(92) near text "endgenerate"; expecting "end" Error (10112): Ignored design unit "Correlation" at Correlation.v(7) due to previous errors  Can any of you gives me some hints on what causes this compilation error?   Thanks  -Roger

[Altera_Forum]

The generate construct, as well as module instantiations and defparams, cannot be inside an always block.

[Altera_Forum]

I have tried to remove the always block, and it shows the same error messages. I guess the reason that causes this is SW[6:0] is a variable not a constant expression. So I guess it cannot pass the static elaboration? What I am interested to know is that is there a way to instantiate the same module with different set of parameters based on an input register value. As I showed in the above example, when the input register value is 7'b0, I will parameterize NUM_PULSE TO be 1 and SAMPLES_PER_CYCLE to be 8, while the input register value is 7'b1, I will parameterize NUM_PULSE TO be 1 and SAMPLES_PER_CYCLE to be 16, etc. I would really appreciate your guidance on this if you have a solution. 

 Thanks,  -Roger

[Altera_Forum]

--- Quote Start ---  is there a way to instantiate the same module with different set of parameters based on an input register value  --- Quote End ---    No way. Module parameters as well generate expressions must be constants. Parameters define the hardware structure and logic wiring which can't be dynamically redefined.   You need to redesign the module to take e.g. SamplesPerCycle as a variable input. A parameter may specify the maximum sample count or the variable width.

[Altera_Forum]

I believe you need to learn how to design hardware first, then learn how to describe that hardware in Verilog. You can design hardware that dynamically responds to certain inputs in a specific way, but you can not change the specification dynamically - that is static.

[Altera_Forum]

Got you. Thank you for the reply.