Generated clock constraint - not a pll or mux clock

[tedh4ddv]

I need to double the frequency of a clock, but the source is not a clock pin, so I am unable to use a PLL.  I opted to use a shift-register and exclusive-OR gate, instead.  Should the high-speed clock driving the shift-register (hs_clk) or the original clock being doubled (clk_in) be assigned as the 'SOURCE' in the constraint? 

[SyafieqS]

In this scenario, the constraint's 'SOURCE' should be set to the high-speed clock (hs_clk) driving the shift-register.

This is because the frequency of the high-speed clock (hs_clk) and the number of stages in the shift-register both affect the frequency of the clock that is being multiplied (clk_in). The output frequency (clk_in) will increase when the shift-register and XOR gate are used to double the frequency of hs_clk. The high-speed clock driving the shift-register must therefore be correctly restricted when the clock network is constrained, and the constraints must also take into account the frequency of clk_in that results.

[SyafieqS]

Let me know if there is any update or concern regarding this

[tedh4ddv]

Given that the clock to be frequency-doubled is "clk_in" and the shift-register clock is "hs_clk", can you provide an example of the generated clock constraint statement for "clk_x2" that would accomplish this?  Specifically, if "hs_clk" is treated as the source, as you suggest, then is the "multiply_by 2" argument not required since I am not doubling the frequency of "hs_clk"?  

[SyafieqS]

Can you share your constraint here? What is the constraint specify in the design.

Snippet would be enough

[tedh4ddv]

The following is the constraint I used, but I don't see how Quartus will relate this to the high-speed clock driving the shift-register.

create_generated_clock -name cvbs1_clk_2x -source [get_pins {p0_out|mux0_clock|combout}] -multiply_by 2 [get_pins {ifb_dec|clkx2_1|clk_2x|q}]

[SyafieqS]

Let me know if there is any update

[SyafieqS]

Let me check this and get back to you

[SyafieqS]

Below is my answer to address you question:

1. Given that the clock to be frequency-doubled is "clk_in" and the shift-register clock is "hs_clk", can you provide an example of the generated clock constraint statement for "clk_x2" that would accomplish this?  

- You can use the following general format:

create_generated_clock -name clk_x2 -multiply_by 2 [get_pins <output_pin_of_shift_register>]

Note that you should replace "<output_pin_of_shift_register>" with the name of the output pin of your shift-register that is connected to clk_in.

2. Specifically, if "hs_clk" is treated as the source, as you suggest, then is the "multiply_by 2" argument not required since I am not doubling the frequency of "hs_clk"? 

- Regarding your second question, if hs_clk is treated as the source clock in your constraint, then you do not need to include a "multiply_by 2" argument because it is already being doubled by the shift-register and XOR gate. The generated clock constraint simply tells Quartus that clk_x2 is derived from hs_clk and has double its frequency.