Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Generating netlist for formal verification

Altera_Forum
Honored Contributor II
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I'm trying to generate a netlist for formal verification and not having much success. 

 

Has anyone succeeded in compiling with a formal verification netlist selected? 

 

Or given it up for dead? 

 

If you succeeded, did you choose the conformal or the custom option? 

 

Can you share the settings that worked? 

 

Ed
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