Generation of STP file for SignalTap

[KAkyo]

Hello,

There is a locking issue in my application on FPGA board and I want to debug my application. When doing research, I found SignalTap is used to follow the signals in the application. I played around Quartus GUI, however I couldn't find a way to generate the STP file. I want to check the signals with the name on RTL files and to do that I have to enable Pre-Synthesis option. I tried that also, but found no signals. I am a newbie about all these tools.

I am working on VLAB, and basically I want to create STP file and check the signals. Is there any way to generate that file automatically for the application (It can be all the signals, only the signals between the modules... anything), and from terminal on VLAB (Because on my local computer RAM is the issue and while fitting shuts down Quartus.) If you can help me, I will appreciate it ( because I am trying to find the problem for a month).

Thank you,

Kaan Akyol

[JOHI]

Hello,

If you start using signaltap logic analyser it generates .stp as a result of your configuraton in signaltap. (make a configuration and save it)

You will have trouble finding some signals in the node list, to solve this you can define the attribute "keep" in your code, then some invisible nodes will become visible with their orignial name.

Example:

-- declare -- attribute keep: boolean; signal reset_p : std_logic:='0'; signal done : std_logic:='0'; signal enable : std_logic:='0';   attribute keep of reset_p : signal is true; attribute keep of done : signal is true; attribute keep of enable : signal is true;

For your problem you might consider using modelsim and write a simulation bench.

This enables you to simulate your design. This approach can be much more productive than signaltap.

On the other hand: are you 100% sure that ram is the issue with Quartus?

Of course it depends on the size of your design, but Quartus runs well in 8GB ram for small designs.

Best Regards,

Johi.

[sstrell]

As mentioned, the op wants to use pre-synthesis signals. As such, keep is not necessary since just the addition of Signal Tap to the design and tapping the signals will preserve them.

In any case, it's much easier to create a .stp file (File menu -> New or from the Tools menu) and add signals from your design to the file. You have to perform at least Analysis & Elaboration (Processing menu) of your design's source code before you will be able to tap the signals in the .stp file Node List. See this online training (and its follow-ups) for everything you need to know about Signal Tap:

https://www.intel.com/content/www/us/en/programmable/support/training/course/odsw1164.html