HLS not generating the VHDL output

[NSuku1]

Hi,

I designed a matrix block using Intel HLS and compiled.. But why does it generate the Verilog output instead of VHDL ?

How to make it to generate the VHDL output?

Please help me.

Thanks,

Nivetha

[HRZ]

Intel's OpenCL and HLS compilers have always been generating verilog as their output. I think adding an option for VHDL was in their roadmap somewhere along the lines but it never happened. The word "VHDL" is not used even once in any of Intel's HLS-related guides and hence, I would assume generating VHDL output is not supported.

[NSuku1]

Oh! NO... I was expecting the hls component will output VHDL and I need to integrate with another component written in VHDL. Now, how can I integrate VHDL with Verilog?

Thanks,

Nivetha

[HRZ]

I integrated a VHDL module inside a Verilog top-module once a few years ago using Xilinx ISE. I would assume it would work the same way when integrating a Verilog module in a VHDL top-module in Quartus: you basically just instantiate the Verilog module in the same way you would instantiate a VHDL module in the top-module and the rest will be handled by the IDE.

[Prince_J_Intel]

my be this link can help to integrate verilog code in vhdl.

https://forums.intel.com/s/question/0D50P00003yyNo0SAE/vhdl-and-verilog-how-i-can-connect-together