Handle error:"Connected system ID hash not found on target at expected base address"

[Altera_Forum]

Hi , I get the following error while trying to run C file on fpga using eclipse: 

"Connected system ID hash not found on target at expected base address" (scrrenshot is attached with name lasterror)  I saw online some solution to tick checkbox under "system ID checks" as can be seen in :"ignorecheckbox.PNG" screenshot.  but when I checkthose i get :"downloading elf process failed".  I saw that most people had that problem because they forgot some reset connection but I cant see anything like this. You can see my QSYS under:"qss ss" screen shot.  I really need your help, Im stuck..  Thanks a lot.    (Im using quartus and my board is max10)

[Altera_Forum]

Hi, 

 I have faced the same problem and it was because of reset problem. In design, I have used a switch for reset and by default, it was active so FPGA was not able to load the elf.  Can you check the reset switch state and take care of whether reset is active low and active high   Let me know if this has helped resolve the issue you are facing or if you need any further assistance.  Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation)

[Altera_Forum]

You need to add a SystemID block to your Qsys design. This block is used by eclipse to verify that it is connecting to the correct Nios processor (some designs have more than one). 

 You can find this peripheral under "Basic Functions -> Simulation; Debug and Verification -> Debug and Performance -> System ID Peripheral".  Connect this up to your Nios processor data master, and set the 32-bit system ID parameter to a hexadecimal value of your choosing.  ---  More critically, you are also You are also missing the connection between the "debug_reset_request" signal, and the "reset" signal on the Nios processor. This connection is required in order to allow the JTAG debugger to be able to reset the Nios processor and connect to it.  ---  As a final point, make sure your clock and reset are connected to FPGA pins in your project (outside Qsys) and that both pins are running correctly (reset is correct polarity, and clock is ticking).

[Altera_Forum]

edit:This is a response for the first comment, now checking the suggestion in the first comment.Thank you , I'm trying a simple program is saw online: 

" module my_first_niosii (  CLOCK_50,  LEDR ); input CLOCK_50; output [9:0] LEDR; NEEK10_QSYS u0(  .clk_clk (CLOCK_50),  . reset_reset_n (1'b0),  . pio_led_external_connection_export (LEDR)  ); endmodule "   ";(this line :". reset_reset_n (1'b0  ";( used to be :". reset_reset_n (1'b1  but I still get the same problem..  Thanks.

[Altera_Forum]

--- Quote Start ---  You need to add a SystemID block to your Qsys design. This block is used by eclipse to verify that it is connecting to the correct Nios processor (some designs have more than one).  You can find this peripheral under "Basic Functions -> Simulation; Debug and Verification -> Debug and Performance -> System ID Peripheral".  Connect this up to your Nios processor data master, and set the 32-bit system ID parameter to a hexadecimal value of your choosing.  ---  More critically, you are also You are also missing the connection between the "debug_reset_request" signal, and the "reset" signal on the Nios processor. This connection is required in order to allow the JTAG debugger to be able to reset the Nios processor and connect to it.  ---  As a final point, make sure your clock and reset are connected to FPGA pins in your project (outside Qsys) and that both pins are running correctly (reset is correct polarity, and clock is ticking).  --- Quote End ---      Thanks, I got an error in the synthesis&analysis, The error says that I already have a a module in this name (because of the new "system ID"): "Error (10228): Verilog HDL error at neek10_qsys_sysid_qsys_0.v(34): module "NEEK10_QSYS_sysid_qsys_0" cannot be declared more than once"  this pin:"debug_reset_request" is inside the :"Nios processor" (which named "cpu"), so I have difficult time to understand what do you mean.

[Altera_Forum]

The "debug_reset_request" signal comes out of the nios processor (from the JTAG debug module), and should be connected to loop back in to the "reset" input of the Nios processor. This allows the debugger to reset the processor.

[Altera_Forum]

Thank you, I forgot my fpga at work, so Ill check it next week,and I will update. 

 Thanks again.

[ABurd]

I have same problem and currently I not can it to correct. Maybe somebody me can to help? Please.

[LVo001]

Hi Everyone,

I know I'm late to this party, but I just wanted to say that the issue for me was a RESET line not in the correct state. I'm using a custom board so it was a little more difficult to track down. What I did to find the issue was in HDL I forced the reset line to the correct state and everything just worked.

I'm also surprised that a lot of issues on this forum go unanswered. If people came back and just mention their solutions, it would also really help.

This is unrelated, but the more I use Altera, the more I like Xilinx instead. Altera's error message made no sense, the system ID and timestamp mismatach. What does that really mean? Did I screw up the Qsys design? My JTAG debugger is reading the wrong info? I've had this reset issue with Xilinx before, and the error message reads, cannot communicate with target, processor maybe in reset, check power.

Anyway, just my thoughts, have a nice day!