Having trouble simulating the dcfifo Megafunction

[Altera_Forum]

I'm quite sure this information must exist somewhere, but I have searched for quite a while now, cannot seem to find it, and am becoming frustrated. 

 background: I am working on a system verilog project, and I have been using VCS to compile and simulate my design thus far. Alternatively, I like to use ModelSim to compile the design files and/or simulate. I am ultimately using Quartus to program the design onto a MAXV CPLD.  problem: I would like to use an Altera Megafunction to create a FIFO (currently using Quartus 10.1sp1), a dcfifo specifically. Clearly I am not including all necessary files, as I am getting an error when I try to compile my current code:  Error-[URMI] Unresolved modules spififo.v, 65 "dcfifo dcfifo_component( .data (data), .rdclk (rdclk), .rdreq (rdreq), .wrclk (wrclk), .wrreq (wrreq), .wrfull (sub_wire0), .q (sub_wire1), .rdempty (sub_wire2));"  Module definition of above instance is not found in the design.  question: Is there an IP limitation that prevents me from compiling and simulating such a megafunction using an external tool like VCS or ModelSim (I have not yet tried with ModelSim)? If not, then the issue must be that I am not generating the correct files, and/or including them within the project correctly. I feel like I'm going around in circles here, and since I can't seem to find a similar issue from anybody else, I'm afraid I'm probably doing something stupid, ie: trying to do something that is not possible.  Any clarification would be appreciated, such as answering my question, tips of what files need to be included, etc. Thanks in advance.

[Altera_Forum]

I posted some Altera FIFO examples a while back, give those a try ... 

 http://www.alteraforum.com/forum/showthread.php?t=38988  At least this should get you a working Modelsim build.  The example is in VHDL, but a verilog design would be similar. If you still cannot get something working, post a simple verilog testbench and I'll get it to work.  Cheers, Dave

[Altera_Forum]

Thanks for the quick response Dave. Honestly, I think the issue I'm having is that I'm not including any of the altera megafunction libraries. In your example, you include them with the following: 

 library altera_mf; use altera_mf.altera_mf_components.all;  I can't however seem to find a similar package to include for system verilog. Do you have any insight into this?

[Altera_Forum]

--- Quote Start ---   I can't however seem to find a similar package to include for system verilog. Do you have any insight into this?  --- Quote End ---    You would need to pass a library argument to vsim, eg., vsim -L altera_mf, or perhaps altera_mf_ver if that is what it is called.  The machine I am typing on now has Quartus 12.1sp1 Web edition, and in its Modelsim-ASE folder is ...  C:\software\altera\12.1sp1_free\modelsim_ase\altera\verilog\altera_mf  so I think vsim <testbench> -L altera_mf is probably what you want.  Cheers, Dave

[Altera_Forum]

Sounds reasonable, since the issue clearly stems from the tool not being able to resolve the dcfifo module. 

 Since I'm primarily working on a system that has VCS installed, and not any Altera collateral, I tried dumping the /verilog/altera_mf/dcfifo file into an area, and including the files with a command line option when calling VCS. I'm not having any luck so far, but have ran out of time to play with it. I'll have to wait until next Tuesday to spend more time on it.  Thanks again for the help, I'll provide some feedback when I get a chance.

[Altera_Forum]

--- Quote Start ---   Since I'm primarily working on a system that has VCS installed   --- Quote End ---   I'm not sure what the commands are for VCS, but in Modelsim-SE the equivalent steps would be;  1. Create and map an altera_mf library  2. Compile altera_mf_components.v into that library  3. Compile your testbench  4. Simulate your testbench and point to the altera_mf library  Cheers, Dave

[Altera_Forum]

Looks like including the altera_mf.v file did it. Thanks for the help!

[Altera_Forum]

--- Quote Start ---  Looks like including the altera_mf.v file did it. Thanks for the help!  --- Quote End ---   Glad to have helped!  Cheers, Dave