module dfftest(
input wire in1;
input wire in2;
output wire out1;
wire SYNTHESIZED_WIRE_7;
wire SYNTHESIZED_WIRE_8;
wire SYNTHESIZED_WIRE_4;
assign SYNTHESIZED_WIRE_7 = 1;
assign SYNTHESIZED_WIRE_8 = 1;
dff2_0 b2v_inst(
.CLK(in2),
.D(in1),
.PRN(SYNTHESIZED_WIRE_7),
.CLRN(SYNTHESIZED_WIRE_7),
.Q(SYNTHESIZED_WIRE_4)
);
jkff2_1 b2v_inst2(
.K(SYNTHESIZED_WIRE_8),
.CLRN(SYNTHESIZED_WIRE_8),
.CLK(SYNTHESIZED_WIRE_4),
.PRN(SYNTHESIZED_WIRE_8),
.J(SYNTHESIZED_WIRE_8),
.Q(out1));
endmodule
module dff2_0(CLK,D,PRN,CLRN,Q);
/* synthesis black_box */
input CLK;
input D;
input PRN;
input CLRN;
output Q;
endmodule
module jkff2_1(K,CLRN,CLK,PRN,J,Q);
/* synthesis black_box */
input K;
input CLRN;
input CLK;
input PRN;
input J;
output Q;
endmodule
