Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Hi, Have been able to add the qsys ADC module to the project but on final compilation the flow summary reports 0/1 ADC blocks in use even after I have selected all ports ANA1IN1 to ADC1IN8 in the qsys window.

AKohl3
初学者
7,165 次查看

 From what i can tell the ADC module only needs a command to select which port to sample so how do i make pin assignments to confirm the ADC in use!  

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1 解答
SreekumarR_G_Intel
6,749 次查看

Hello there ,

Here attached the screen shot and the modfied design file with ADC block utilization mentioned in the compliation report.

As of understood from the design you provided , quartus is optimizing the ADC block since it is no where used in the design.

 

In the modified design i instantiated the ADC input and clock as Input port which restrict the quartus to optimize the same.

 

ADC_Block.PNG

Hope helps ,

 

Thank you ,

 

Regards,

Sree

在原帖中查看解决方案

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AKohl3
初学者
2,301 次查看

Hi,

Looking forward to your reply!

 

Avdit

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SreekumarR_G_Intel
2,301 次查看

can I know did you get a chance to figure it the issue ? if you still facing the issue kindly let me know ?

 

Thank you,

 

Regards,

Sree

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SreekumarR_G_Intel
2,301 次查看

sorry , didnt see your updated post ; Can I know you still facing the issue ?

 

Thank you ,

 

Regards,

Sree

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AKohl3
初学者
2,301 次查看

Yes Sree, I am still facing the same issue besides I have attached all files you requested in the past. Can you please provide an solution to the above attached project file as soon as possible?

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SreekumarR_G_Intel
2,301 次查看

sorry, i didnt noticed your reply , can i know is that issue resolved ? kindly let me know if you looking for my design files still.

Apologize my delay in response.

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SreekumarR_G_Intel
2,301 次查看

Hello , I thought i attached the file to you , Sorry looks i missed out, Can i know you still facing the same issue ? if yes , i will look at again .

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AKohl3
初学者
2,301 次查看

Hi,

I am still facing the same problem. I have been able to check the ADC input if I invoke the Jtag avalon adapter but if I use just the ADC control core the response data is stuck at zero. In the attached project I am trying a simple led blink check using the output of the ADC module. I would really appreciate a prompt reply.

 

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SreekumarR_G_Intel
6,750 次查看

Hello there ,

Here attached the screen shot and the modfied design file with ADC block utilization mentioned in the compliation report.

As of understood from the design you provided , quartus is optimizing the ADC block since it is no where used in the design.

 

In the modified design i instantiated the ADC input and clock as Input port which restrict the quartus to optimize the same.

 

ADC_Block.PNG

Hope helps ,

 

Thank you ,

 

Regards,

Sree

0 项奖励
SreekumarR_G_Intel
2,301 次查看

hello ,

sorry , I completed missed that your case here.

can you let me know you still facing the same issue , if yes I can attach the design which another customer posted the same in fourm.

 

Thank you ,

 

Regards,

Sree

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