How can I change an I/O pin's pull_up value without re-synthesizing the design?

[KOber]

I need to change whether or not there are weak pull_ups on an FPGA's I/O pin but don't have the privilege of re-compiling the whole design.

A new gateware file would need to be created, but since we are just changing an IOB setting, there should be a way to make that specific modification post synthesis.

How can I do that?

I am using Quartus Prime Standard 19.1.0 and am building gateware for an Arria 10 FPGA.

[ShafiqY_Intel]

Hi KOber,

Apparently, pull up the I/O without re-synthesizing the design is not possible.

You can only pull up it using Pin Planner or Pin assignment. Then you have to compile it to create a new bit stream.

Thanks

[KOber]

ShafiqY_Intel,

Can you put in an Arria 10 feature request for the ability to add pull ups to I/O without re-synthesizing the design, and provide me with the change request number?

Thank you

[KOber]

ShafiqY_Intel,

What is the Change Request Number for this feature request?

> Can you put in an Arria 10 feature request for the ability to add pull ups to I/O without re-synthesizing the design, and provide me with the change request number?