How can I know what compiled libraries needed for my design simulation?

[Altera_Forum]

I make design in Quartus II. Then I need simulate it in Modelsim. I don't want to use the Quartus nativelink to run Modelsim for simulation. I prefer to do is creating the simulation project, add the design files into project and do simulation.  

 However, there is a problem that I need to add needed compiled libraries before I can do simulation (as attachment showed). In normal case, the design needs multiple libraries.So how can I know what compiled libraries I need for simulation? Or is there any other approach that I don't need to add the libraries one by one manually?  Thanks a lot.

[Altera_Forum]

If you install Modelsim Altera or Starter edition, it comes with all the libraries pre-compiled for you. Either map to them manually, or copy and paste then entries out of the modelsim.ini file into your other version of modelsim's ini file.

[Altera_Forum]

--- Quote Start ---  If you install Modelsim Altera or Starter edition, it comes with all the libraries pre-compiled for you. Either map to them manually, or copy and paste then entries out of the modelsim.ini file into your other version of modelsim's ini file.  --- Quote End ---    Hi Tricky, thanks very much for your answer. But it seems you misunderstood my question. I already compiled libraries and map them to Modelsim.   My question is when I want to simulate a design in Modelsim, I create a project and create a simulation configuration file as the attached image, in this interface, it asks me to add libraries, how can I know which libraries I needed to add, for my design simulation?

[Altera_Forum]

Are you talking about HDL simulation or post place and route simulation? 

 FOr HDL sim you just compile all the files with vcom(vhdl) or vlog(verilog) and then vsim the component (the testbench) you want to simulate. libraries can be setup with vlib and Vmap. Modelsim project files are a waste of time.

[Altera_Forum]

--- Quote Start ---  Are you talking about HDL simulation or post place and route simulation?  FOr HDL sim you just compile all the files with vcom(vhdl) or vlog(verilog) and then vsim the component (the testbench) you want to simulate. libraries can be setup with vlib and Vmap. Modelsim project files are a waste of time.  --- Quote End ---     Thanks, Tricky. So I think you suggested me to use tcl command instead of using GUI. Let me make my question more clear. I need to do simulation in both HDL level and Post PR level.  In most cases, my designs adopts many soft IP cores (PCIe, FIR, Coding and decoding). My designs also adopts some hard IP cores (Gigbit transceivers). And my designs will be in a series device, e.g, Starix V.  If I want to simulate in HDL levels, based on my understanding I need assign libraries, which Modelsim needed, for simulation. If I want to simulate in Post PR level, I also need to assign libraries in Modelsim, but these libraries may be different from which needed in HDL simulation. This is my understanding, it may be wrong?  So now my question is: there are so many compiled libraries in Modelsim, how can I know which are needed for my designs? Does this must be done by manually? Or there is a better approach, that can be done automatically?

[Altera_Forum]

BTW, I want to learn how to use script to do simulation in Modelsim. Is there some good example script which do some simple operation I can learn? 

 Thanks very much.

[Altera_Forum]

the easiest thing to do is just map all of the altera libraries in your modelsim.ini file, then all libraries are available to all compilations all the time. but here is a quick tcl file that should set them all up from wherever you are. 

   set LibPath C:/altera/modelsim/modelsim_ae/altera vlib altera_mf vlib altera vlib lpm vlib 220model vlib max vlib maxii vlib stratix vlib stratixii vlib stratixiii vlib stratixiv vlib stratixv vlib cyclone vlib cycloneii vlib cycloneiii vlib sgate vlib stratixgx vlib altgxb vlib stratixgx_gxb vlib altera_mf_ver vlib lpm_ver vlib 220model_ver vlib alt_ver vlib max_ver vlib maxii_ver vlib stratix_ver vlib stratixii_ver vlib stratixiii_ver vlib stratixiv_ver vlib stratixv_ver vlib cyclone_ver vlib cycloneii_ver vlib cycloneiii_ver vlib sgate_ver vlib stratixgx_ver vlib altgxb_ver vlib stratixgx_gxb_ver vmap altera_mf $LibPath/vhdl/altera_mf vmap altera $LibPath/vhdl/altera vmap lpm $LibPath/vhdl/220model vmap 220model $LibPath/vhdl/220model vmap max $LibPath/vhdl/max vmap maxii $LibPath/vhdl/maxii vmap stratix $LibPath/vhdl/stratix vmap stratixii $LibPath/vhdl/stratixii vmap stratixiii $LibPath/vhdl/stratixiii vmap stratixiv $LibPath/vhdl/stratixiv vmap stratixv $LibPath/vhdl/stratixv vmap cyclone $LibPath/vhdl/cyclone vmap cycloneii $LibPath/vhdl/cycloneii vmap cycloneiii $LibPath/vhdl/cycloneiii vmap sgate $LibPath/vhdl/sgate vmap stratixgx $LibPath/vhdl/stratixgx vmap altgxb $LibPath/vhdl/altgxb vmap stratixgx_gxb $LibPath/vhdl/stratixgx_gxb vmap altera_mf_ver $LibPath/verilog/altera_mf vmap altera_ver $LibPath/verilog/altera vmap lpm_ver $LibPath/verilog/220model vmap 220model_ver $LibPath/verilog/220model vmap max_ver $LibPath/verilog/max vmap maxii_ver $LibPath/verilog/maxii vmap stratix_ver $LibPath/verilog/stratix vmap stratixii_ver $LibPath/verilog/stratixii vmap stratixiii_ver $LibPath/verilog/stratixiii vmap stratixiv_ver $LibPath/verilog/stratixiv vmap stratixv_ver $LibPath/verilog/stratixv vmap cyclone_ver $LibPath/verilog/cyclone vmap cycloneii_ver $LibPath/verilog/cycloneii vmap cycloneiii_ver $LibPath/verilog/cycloneiii vmap sgate_ver $LibPath/verilog/sgate vmap stratixgx_ver $LibPath/verilog/stratixgx vmap altgxb_ver $LibPath/verilog/altgxb vmap stratixgx_gxb_ver $LibPath/verilog/stratixgx_gxb

[Altera_Forum]

The key commands you need are: 

 vcom/vlog <somefile> -- VHDL/Verilog compile command. Will by default compile into the work library, but using the -work option you can chose what library to compile into vsim <my_design_unit> -- starts the simulation of the design  run X ns -- run simulation for X ns (-all option just runs forever until testbench stops) vlib <some_library> -- creates a library vmap <some_library> <libary_directory> -- maps a libaray to the specified directory do <somefile> -- runs a tcl script  Thats about all the commands I use. I use the gui for adding waves to a wave window then save it to some .do file that I can then just run later.

[Altera_Forum]

oh, I forgot -  

 restart - restarts a simulation.  you can run vcom/vlog during a simulation, and it will reload the recompiled design after a restart, so you dont have to restart the entire sim via vsim.

[Altera_Forum]

--- Quote Start ---  the easiest thing to do is just map all of the altera libraries in your modelsim.ini file, then all libraries are available to all compilations all the time. but here is a quick tcl file that should set them all up from wherever you are.    set LibPath C:/altera/modelsim/modelsim_ae/altera vlib altera_mf vlib altera vlib lpm vlib 220model vlib max vlib maxii vlib stratix vlib stratixii vlib stratixiii vlib stratixiv vlib stratixv vlib cyclone vlib cycloneii vlib cycloneiii vlib sgate vlib stratixgx vlib altgxb vlib stratixgx_gxb vlib altera_mf_ver vlib lpm_ver vlib 220model_ver vlib alt_ver vlib max_ver vlib maxii_ver vlib stratix_ver vlib stratixii_ver vlib stratixiii_ver vlib stratixiv_ver vlib stratixv_ver vlib cyclone_ver vlib cycloneii_ver vlib cycloneiii_ver vlib sgate_ver vlib stratixgx_ver vlib altgxb_ver vlib stratixgx_gxb_ver vmap altera_mf $LibPath/vhdl/altera_mf vmap altera $LibPath/vhdl/altera vmap lpm $LibPath/vhdl/220model vmap 220model $LibPath/vhdl/220model vmap max $LibPath/vhdl/max vmap maxii $LibPath/vhdl/maxii vmap stratix $LibPath/vhdl/stratix vmap stratixii $LibPath/vhdl/stratixii vmap stratixiii $LibPath/vhdl/stratixiii vmap stratixiv $LibPath/vhdl/stratixiv vmap stratixv $LibPath/vhdl/stratixv vmap cyclone $LibPath/vhdl/cyclone vmap cycloneii $LibPath/vhdl/cycloneii vmap cycloneiii $LibPath/vhdl/cycloneiii vmap sgate $LibPath/vhdl/sgate vmap stratixgx $LibPath/vhdl/stratixgx vmap altgxb $LibPath/vhdl/altgxb vmap stratixgx_gxb $LibPath/vhdl/stratixgx_gxb vmap altera_mf_ver $LibPath/verilog/altera_mf vmap altera_ver $LibPath/verilog/altera vmap lpm_ver $LibPath/verilog/220model vmap 220model_ver $LibPath/verilog/220model vmap max_ver $LibPath/verilog/max vmap maxii_ver $LibPath/verilog/maxii vmap stratix_ver $LibPath/verilog/stratix vmap stratixii_ver $LibPath/verilog/stratixii vmap stratixiii_ver $LibPath/verilog/stratixiii vmap stratixiv_ver $LibPath/verilog/stratixiv vmap stratixv_ver $LibPath/verilog/stratixv vmap cyclone_ver $LibPath/verilog/cyclone vmap cycloneii_ver $LibPath/verilog/cycloneii vmap cycloneiii_ver $LibPath/verilog/cycloneiii vmap sgate_ver $LibPath/verilog/sgate vmap stratixgx_ver $LibPath/verilog/stratixgx vmap altgxb_ver $LibPath/verilog/altgxb vmap stratixgx_gxb_ver $LibPath/verilog/stratixgx_gxb   --- Quote End ---    Thanks very much. So I can write all of these commands in my .do file. And execute it before I do simulation, right?

[Altera_Forum]

you should only need to map those libraries once. It should place them in the modelsim.ini file

[Altera_Forum]

--- Quote Start ---  you should only need to map those libraries once. It should place them in the modelsim.ini file  --- Quote End ---    Thanks, so that means everytime I run modelsim, then these libraries will be automatically mapped to my working library. I will try to use command, if I have questions, I will post here.  Thanks.

[Altera_Forum]

I found it seems I described my question not clear. What I really want to ask is: when I simulate a design, how can I know what resource libraries needed to link? The resource libraries are libraries from Altera and I compiled them in Modelsim. I need to link the needed resource libraries when I simulate my designs. 

 Thanks very much.

[Altera_Forum]

you dont need to know, as long as they are mapped in modelsim, you can access them from VHDL.

[Altera_Forum]

--- Quote Start ---  you dont need to know, as long as they are mapped in modelsim, you can access them from VHDL.  --- Quote End ---    Thanks, Tricky. What do you mean I can acess them from VHDL? When I programed, they are listed in my VHDL code?  And how about if I program using Verilog?

[Altera_Forum]

Using VHDL, you map libraries directly: 

  library some_library; use some_library.some_package.all; .... --direct instantiation some_inst : entity my_library.some_entity(ent_arch) generic map () port map (); --etc   So as long as you have the libraries mapped in modelsim, you write code like the above to access them. If they are not mapped, you'll get and error when you compile.  Verilog has no idea of libraries, so it will primarily search the work library for a design unit. YOu can add libraries to the search with the -L option on vsim:  vsim some_entity -L library1 -L library2 etc

[Altera_Forum]

--- Quote Start ---  Using VHDL, you map libraries directly:   library some_library; use some_library.some_package.all; .... --direct instantiation some_inst : entity my_library.some_entity(ent_arch) generic map () port map (); --etc   So as long as you have the libraries mapped in modelsim, you write code like the above to access them. If they are not mapped, you'll get and error when you compile.  Verilog has no idea of libraries, so it will primarily search the work library for a design unit. YOu can add libraries to the search with the -L option on vsim:  vsim some_entity -L library1 -L library2 etc  --- Quote End ---    "vsim some_entity -L library1 -L library2"&#65292; this is what I want to ask. I have to add these libraries otherwise I can't simulate. However, for a specific design, how can I know what libraries I need? E.g. I make a design in a cyclone IV chip with some IPs: FIFO, PLL. I know I need cycloneiv_ver, and what libraries need for IPs like FIFO, PLL? How can I know that?  Now the approach I take is: I run the simulate through nativelink, and check the generated .do file to read the command. Anyother better approach?  And for VHDL design, do I need to add libraries with command:   vsim library1 library2 ……  Thanks.

[Altera_Forum]

you only need the -L for verilog code as verilog has no knowledge of libraries, so the -L tells it where to search for modules. For VHDL you dont need any -L arguments because you already mapped them in the code. 

 Generally you only use the altera_mf library, as that is where most of the IP lives. That library will call in items from cyclone IV or wherever depending on the generics on the blocks. But if you are missing something, it will tell you (and in VHDL it will tell you which library it cannot find). The only way to really know what libraries you need is by looking at the code.  I have never used nativelink, or a generated .do file, I always do simulations manually.

[Altera_Forum]

You mentioned that "Generally you only use the altera_mf library, as that is where most of the IP lives." So if my design want to use some common IPs, I need to map the altera_mf library at the beginning of my VHDL code as: 

 library altera_mf   Right? All the libraries I need to use I need map at the beginning of the VHDL codes, right?  Thanks.

[Altera_Forum]

ues, plus add the line 

use altera_mf.altera_mf_components.all;

[Altera_Forum]

Thanks very much, Tricky.