My signaltap file has:
If I make a change to the trigger such as:
"Disable Storage Qualifier"
Change one of the "BASIC OR" trigger from rising edge to don't care.
And then "Run analysis" on the instance I get the dreaded "not compatible with the device" error.
However if I close the project and re-open it (making no changes) it runs ok.
I then made the change and saved the .stp file with a different file name.
I did a diff on the new file and noticed that the CRC had changed.
I edited the CRC back to the old value (from the original working .stp file) and opened the edited file in the analyzer - it runs fine.
I was playing about with settings such as "Power up trigger" and "trigger input from another instance" but turned these off and didn't save these.
So I concluded that something in the analyzer software is calculating the CRC incorrectly and it thinks there is a mismatch between the FPGA and the analyzer settings.
Probably something was added to the .stp file when I was trying out the power up / trigger input settings.
How can I fix this?
To know what you shouldn't change to cause a recompile, enable the trigger condition lock mode at the top of the node list. This will prevent you from making changes that will require a recompile and keep your .stp compatible with the current hardware implementation of the logic analyzer.
Thanks for the reply but that was one of the first things I tried.
Needless to say it didn't work.
However, I know the change I made is allowed. You can change a trigger signal from rising edge to don't care without a re-compile else what use is the tool?
What version of Quartus that you had used? There are some workaround for older version of Quartus if you face this error:
Also, can you put a screenshot here so that we can see what is missing in your signal tap? Yes, changing the trigger condition does not require you to full recompile of the design.
One things to note that, it is always advise that you have make your timing close before doing the hardware test. Had you make sure that your timing sdc was written correctly and the timing close?