How to constraint min delay between LCELLs?

[NuvKFC]

Some asynchronous need to use LCELLs to generate pulses, like following example.

However, the delay of LCELLs is different on the difference FPGA device.

So, I use following constraints to constraint the min delay of LCELL. 

But it doesn't work.

How to constraint min delay between LCELLs?

Thank you very much.

Ex.:

lcell dly1d (.out(y1), .in(A) );

lcell dly4d (.out(y), .in(y1) );

Constraints:

set_min_delay 5.0 -from [get_pins dly1d|combout] \

                                  -to      [get_pins dly4d|combout]

set_net_delay -min 5.0  -from [get_pins dly1d|combout] \

                                            -to      [get_pins dly4d|combout]

[NuvKFC]

Hi Nurina
    Thank you, Nurina, very much.

OK. I  get it. Thank you very, very much. ^.^

[NuvKFC]

Hi Nurina
    Thank you, Nurina, very much.

Sorry that I have a question.

Using set_min_delay need a setup/hold relationship on that path.

Why set_net_delay can't work on LCELLS?

[Nurina]

Hello,

Just like set_max/min_delay, set_net_delay requires the path to have a setup/hold relationship (reg to reg path). So it doesn't go through comb logic.

Regards,

Nurina

[NuvKFC]

Hi Nurina
    Thank you, Nurina, very much.

OK, I get it. Thank you very, very much.

[Nurina]

Hello,

No problem! I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

Regards,

Nurina

P/S: If you like my comment, feel free to give Kudos. If my comment solved your problem, feel free to accept my comment as solution.

[NuvKFC]

Hi Nurina
    Thank you, Nurina, very much.

OK. No problem! Thank you very, very much.