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Unconstrained I/O when using design partitions

VCham
New Contributor I
880 Views

Hello I am doing late floorplanning and have started with setting up design partitions. 

To start I have a single partition set to post-fit.

 

My issue is that upon compilation, I get a ton of unconstrained i/o from the new partition. What is the correct way to constrain these i/o? I'm only familiar with constraining top level i/o

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sstrell
Honored Contributor III
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Can you explain what is complete in your design?  When you say I/O, those are usually top-level, so it's not clear what you mean by unconstrained I/O that are not top-level.

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VCham
New Contributor I
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Before attempting partitioning, my design was fully complete. There were zero unconstrained I/O. Timing was being met.

 

When I added a design partition, the TimeQuest Analyzer reported 46 unconstrained output ports. Looking at the signals they are just an avalon memory mapped address bus that is an input to the partition. I am not sure why it's being called out as unconstrained. 

VCham_0-1653575534460.png

 

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AqidAyman_Intel
Employee
835 Views

Hi Valentina,


What device is you using and which edition of Quartus?


Regards,

Aqid


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VCham
New Contributor I
826 Views

Quartus II Standard 17.0.2

Cyclone V

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sstrell
Honored Contributor III
802 Views

So your design was complete and you simply set part of it as a design partition, recompiled, and got this?  Can you show your design partition settings/assignments?  For some reason, the connections from your design partition to the root partition of your design are missing.  Simply setting an entity as a design partition should not cause this to happen.  You're not using virtual pin assignments, are you?

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VCham
New Contributor I
791 Views

Since my last post I've tried the autopartitioner to help with different issues. But I'm still getting the same unconstrained paths.

These are the current partition settings. I am not using any virtual pins.

VCham_0-1654008398260.png

 

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AqidAyman_Intel
Employee
775 Views

Hi,


Can you try the steps to size and and place regions after compilation as in Best Practices for Incremental Compilation Partitions and Floorplan Assignments page 15-45?


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AqidAyman_Intel
Employee
739 Views

Hi Valentina,


Any updates on the status from your side? Does it resolve your issue?


Regards,

Aqid


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AqidAyman_Intel
Employee
723 Views

We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

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