Hello I am doing late floorplanning and have started with setting up design partitions.
To start I have a single partition set to post-fit.
My issue is that upon compilation, I get a ton of unconstrained i/o from the new partition. What is the correct way to constrain these i/o? I'm only familiar with constraining top level i/o
Can you explain what is complete in your design? When you say I/O, those are usually top-level, so it's not clear what you mean by unconstrained I/O that are not top-level.
Before attempting partitioning, my design was fully complete. There were zero unconstrained I/O. Timing was being met.
When I added a design partition, the TimeQuest Analyzer reported 46 unconstrained output ports. Looking at the signals they are just an avalon memory mapped address bus that is an input to the partition. I am not sure why it's being called out as unconstrained.
So your design was complete and you simply set part of it as a design partition, recompiled, and got this? Can you show your design partition settings/assignments? For some reason, the connections from your design partition to the root partition of your design are missing. Simply setting an entity as a design partition should not cause this to happen. You're not using virtual pin assignments, are you?
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