How to extract 1bit from a bus in a Block Diagram/Schematic File

[Altera_Forum]

Well, I'm new to quartus and I don't know if this is possible or not. i can handle it in verilog/vhdl but I wanted to know if this can be done in a block diagram file. 

 This is what I want to do: (Example)  I've implemented a lpm_add_sub as an 8 bit adder, how can I for example use bit 2 & 3 of the output as inputs of another gate?(I need to extract these 2 bits out of the output )  I hope what I've said is clear enough.  Thanks in advance.

[Altera_Forum]

Select the bus and type a name for the bus like: result[8..0] 

 Then, using the Orthogonal Node tool, create a line, select the line (signal) and type a name for the signal like: result[5]. This signal is the bit 5 of the bus result[8..0].   (Sorry for the bad english, i'm brazilian):)   Rodrigo Willians

[Altera_Forum]

--- Quote Start ---  Select the bus and type a name for the bus like: result[8..0]  Then, using the Orthogonal Node tool, create a line, select the line (signal) and type a name for the signal like: result[5]. This signal is the bit 5 of the bus result[8..0].   (Sorry for the bad english, i'm brazilian):)   Rodrigo Willians  --- Quote End ---   Thanks buddy! That's what I needed!  I, myself am from Iran!

[Altera_Forum]

Good and clear. 

One principle: always name the wider bus first, then name the narrower bus accordingly. By the way, I am Chinese.

[Altera_Forum]

--- Quote Start ---  Good and clear. One principle: always name the wider bus first, then name the narrower bus accordingly. By the way, I am Chinese.  --- Quote End ---   Thankyou !