How to fix BDF Text Scaling Bug when Windows Scaling active?

[SMatl]

Since years and versions, Quartus fails on creating correct Text-Frame-Sizes on BDF Files when Windows-Scaling (125%) ist active. When (or how) will this be fixed? It is a catastrophic pain to guess the ending of all signals, both on blocks or wires as to see on the screenshot, Thank you!

[KhaiChein_Y_Intel]

Hi,

May I know what edition (Pro/Standard) and version you are using?

Thanks.

Best regards,

KhaiY

[SMatl]

I'm using the Lite Version, but we also have several "Standard" licences as well as far as i know. (As I'm also working with students, i prefer the Lite Version.) Would that matter? ;)

[KhaiChein_Y_Intel]

Hi,

This is not related to license. I asked the software edition because I want to try to duplicate the error.

You may change the DPI to 96, follow by restarting your computer.

To change the DPI setting: Desktop > Right Click > Display Settings > Display Tab > Change the size of text,apps, and other items.

KDB: https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/solutions/spr360409.html

Thanks.

Best regards,

KhaiY

[SMatl]

Thank you for help. Ok, Intel seems to know the problem. When or How will this Bug be fixed? Are your customers programming on 15" Super-VGA displays only ;)? Scaling technology is known since at least 20 Years i guess. (Win XP or ME?) On my machines, a Surface (150% Scaling) as well as PC with UHD Monitor(s) (125% and 200% scaling), "96 DPI" is kind of technically impossible. (You mean 100% scaling, i guess - changing DPI on LCD is more or less physically/technically impossible)

Anyhow, as the rendering of all elements and letters is fine, so i would state, there is only a small function, the calculation of the text-frame-size, buggy. Would you please ask to update or Bugfix this? Thank you very much :)

[KhaiChein_Y_Intel]

Hi,

The latest version of the software does not support Block diagram anymore. Customer is advised to use the workaround in the KDB if customer is using older software.

Thanks.

Best regards,

KhaiY

[SMatl]

Ah, ok, that is very interesting information.

That information seems to be important for my 96 DPI-colleagues as well. Do you have a link for sharing announcing this and these kind of changes? Is there an alternative / other tool planned or is it thought to use Platform Designer Tool instead?

Thank you very much!

[KhaiChein_Y_Intel]

Hi,

Yes. This problem is documented in this KDB https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/solutions/spr360409.html

Platform Designer is different from BDF schematic entry. Platform Deisgner is a system integration tool in the Intel® Quartus® Prime software. The Platform Designer saves significant time and effort in the FPGA design process by automatically generating interconnect logic to connect intellectual property (IP) functions and subsystems. You may also create a custom IP using Platform Designer.

Thanks.

Best regards,

KhaiY