The timing violation is present within the multiplier
-ve slack => -2.335
Thanks in advance!
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Sorry for the delay
The problem is design file cannot be shared.
I would like to receive inputs on how to solve timing issues on irrelevant paths in the system.
I figured out that the problem was not present in the path that is traceable in the design.
System is something like this
a-> b-> c ->d
where a,b,c,d are modules which work in sequence
The timing issue is in
from node : module d
to node : module b
(there is not link between these modules in the design)
Set as False path
I have tried this .
The process is tedious as the SDC has to be updated and the compilation has to be repeated for more number of iterations (time consuming) to achieve frequency.
Is there an alternate way?
If you set false path to the irrelevant path, you will not see the timing analysis on the path and there should be only one time compilation. Do you still see the timing analysis on the same path after you apply false path?
Yes ..i do observe that...
I want to add another point.
I see that one lpm_divide instance used in the design consumes 6k MLAB
And though the timing path is irrelevant , the "to node" points to this divider.
Is there a way i can make the lpm_divide instance (63x63) be forced to implement using M10Ks ?
Will this help in improving the timing?
What is the device you are using? It is difficult to fix timing violation without looking into the design. Kindly provide a design.qar or test case that can reproduce the error.
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