How to fix the timing violation with an IP (altera_mult_add)

[SKGR0]

The timing violation is present within the multiplier

-ve slack => -2.335

From node

mult_2_64x8:lsm_mult3_inst|lsm_mult_2_64x8_0002:mult_2_64x8_inst|altera_mult_add:altera_mult_add_component|altera_mult_add_n5qg:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_data_split_reg_ext_function:datab_split|ama_latency_function:data0_pipeline_reg_block|data_out_array[1][0]~_Duplicate_1

To Node

mult_2_64x8:lsm_mult3_inst|mult_2_64x8_0002:mult_2_64x8_inst|altera_mult_add:altera_mult_add_component|altera_mult_add_n5qg:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_register_function:output_reg_block|data_out_wire[41]

Thanks in advance!

[KhaiChein_Y_Intel]

Hi,

Can you share the design.qar for investigation? What is the software edition (Standard/Pro) and version you are using?

Thanks.

Best regards,

KhaiY

[SKGR0]

Hi

Version used - Quartus II Standard 16.1.203

I might not be able to share .qar file

Regards

Sahana

[KhaiChein_Y_Intel]

Hi Sahana,

I have sent you an email for private discussion. Let me know if you do not receive.

Thanks.

Best regards,

KhaiY

[KhaiChein_Y_Intel]

Hi Sahana,

May I know if you have any udpates?

Thanks.

Best regards,

KhaiY

[KhaiChein_Y_Intel]

Hi Sahana,

We do not receive any response from you to the previous question/reply/answer that I have provided. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.

Thanks.

Best regards,

KhaiY

[SKGR0]

Sorry for the delay

The problem is design file cannot be shared.

I would like to receive inputs on how to solve timing issues on irrelevant paths in the system.

I figured out that the problem was not present in the path that is traceable in the design.

System is something like this

a-> b-> c ->d

where a,b,c,d are modules which work in sequence

The timing issue is in

from node : module d

to node : module b

(there is not link between these modules in the design)

Regards

SKGR0

[KhaiChein_Y_Intel]

Hi SKGR0,

If there is no timing relationship between the two module or irrelevant path, is it possible to false path ?

Thanks.

Best regards,

KhaiY

[SKGR0]

Hi

Set as False path

I have tried this .

The process is tedious as the SDC has to be updated and the compilation has to be repeated for more number of iterations (time consuming) to achieve frequency.

Is there an alternate way?

Regards

SKGR0

[KhaiChein_Y_Intel]

Hi,

If you set false path to the irrelevant path, you will not see the timing analysis on the path and there should be only one time compilation. Do you still see the timing analysis on the same path after you apply false path?

Thanks.

Best regards,

KhaiY

[SKGR0]

Hi KhaiY

Yes ..i do observe that...

I want to add another point.

I see that one lpm_divide instance used in the design consumes 6k MLAB

And though the timing path is irrelevant , the "to node" points to this divider.

Is there a way i can make the lpm_divide instance (63x63) be forced to implement using M10Ks ?

Will this help in improving the timing?

Regards

SKGR0

[KhaiChein_Y_Intel]

Hi SKGR0,

What is the device you are using? It is difficult to fix timing violation without looking into the design. Kindly provide a design.qar or test case that can reproduce the error.

Thanks.

Best regards,

KhaiY

[KhaiChein_Y_Intel]

Hi,

We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you

Best regards,

KhaiY