How to incorporate a VHDL file within Top level file in Quartus not using Platform Designer

[CPR7]

Hello,

I am somewhat new to FPGA and new to using Quartus IDE. My question is that I could not incorporate  

a file within the top level file that I created even after instantiating the .vhd file inside the top level 

file.  I would like to try to incorporate the file by not using Platform Designer. Is this possible?

Is there any reference that you could recommend that explains all about this.

Thanks in advance and regards.

[FvM]

Hi,
it's not quite clear what you mean with "incorporate a file within the top level file"?

Basically all VHDL files added to your project are compiled and all design entities found therein added to default library work unless explicitely assigned to a different library.

Design entities are "incorporated" to your design by instantiating it in the design hierarchy, starting with the top level entity specified in Quartus project.

The best reference is VHDL language reference IEEE Std. 1076 or a VHDL text book of your choice.

Can you tell how far instantiation of design entities doesn't work for you?

Regards
Frank

[KennyTan_Altera]

Why don't you attached your design.qar files for us to take a look?

Also, for new user, you can try to look into https://community.intel.com/t5/FPGA-Wiki/University-Workshops/ta-p/735639 -> 4. FPGA Simulation & Debug

[CPR7]

Hello gentlemen,

I apologize for the late reply about my problem. Being less experience using the Quartus II IDE my problem is how do I include or add a file to my top level design? I tried to use the option "Add/remove file to the project" but during the compilation process it gave an error with particulars attached. I also attached the top level design. Thank you in advance for your  assistance.

CPR7

[FvM]

Hi,
according to compilation report, the design entity Hex7Seg isn't defined in any VHDL project file. Either the respective file hasn't been added to the project or it doesn't define the design entity correctly. We'd need to see the VHDL code to understand why.

Regards
Frank

[KennyTan_Altera]

Is there further question? If no, we shall close this thread.

[KennyTan_Altera]

Instead of attaching the screenshot, can you attached your design.qar files? Here is the steps: https://www.intel.com/content/www/us/en/docs/programmable/683475/19-4/archiving-projects.html

[CPR7]

Hi Kenny,

 I sent the .qar files but I don't know if they went through. Anyway I am sending again and I hope I sent the ones that you need.

[KennyTan_Altera]

Is there any update for the above?

[KennyTan_Altera]

I don't think it went through, you can check here https://community.intel.com/t5/Intel-Quartus-Prime-Software/How-to-incorporate-a-VHDL-file-within-Top-level-file-in-Quartus/m-p/1685663#M86196

[CPR7]

Hi Kenny,

I'll send them again. Hope it's correct. Thanks.

[FvM]

• Please try to append the .qar file to your post. Use button "Browse files to attach".

[KennyTan_Altera]

Not sure if you have update for the above?

[KennyTan_Altera]

Not sure if you have update for the above?

[KennyTan_Altera]

As we do not receive any response from you on the previous question that we have provided. Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.