Hi. I am new to QSYS and VHDL, so i am still learning. I have created a VHDL code and simulated it in MODELSIM = it works fine, as it should
I have then wrapped it into an avalon MM interface and created a QSYS component = it looks fine
Then I have added generics to my VHDL code to set the base address of the registers/memory in the code. When I create the QSYS module now a aprameter call base_address shows up, but how do i link this parameter to the column called base in the system contents tab? I am guessing this is the same parameter?
As you add the components in the Qsys/platform designer system, you specify their base addresses within the span of the address space using Qsys GUI.
Base address can be directly edited by the user, or it can be assigned automatically by using the Assign Base Addresses from System menu
We can control on the offset address using HDL.
Refer below link
Let me know if this has helped resolve the issue you are facing or if you need any further assistance.
Let me explain with example:
To have better understanding go through course like Using the Nios II Processor: Hardware Development,Using the Nios II Processor: Software Development & Using the Nios II Processor: Custom Components and Instructions
No, the base address column in Platform Designer is the base address of your component as seen from a master connected to your slave. Addresses you set up in your custom component are offsets of this. Remember, every master in the system has its own unique address map. So if you set a base address of, say, 0x1000, in the Platform Designer Base address column, the first register (word) in your component would be accessed by the master at address 0x1000. Depending on the data bus width, the next register (again, word) would be accessed at 0x1002 (for 16-bit data) or 0x1004 (for 32-bit data). The master addressing is byte-wide, which is why I increased by 2 or 4. The slave-side addressing is word-based.
Any generics you use in your custom component code can be optionally customized in the parameter editor when your component is added to the system, but addressing of master-accessible registers in the custom component is not a good idea (or it might even be illegal, not sure). The address map for your component must be fixed at generation time (the End address column in Platform Designer is set by this).
See this online training for all details about creating custom components and their addressing: