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OKris1
Beginner
542 Views

How to set QSYS component base address through VHDL generics

Hi. I am new to QSYS and VHDL, so i am still learning. I have created a VHDL code and simulated it in MODELSIM = it works fine, as it should

 

I have then wrapped it into an avalon MM interface and created a QSYS component = it looks fine

 

Then I have added generics to my VHDL code to set the base address of the registers/memory in the code. When I create the QSYS module now a aprameter call base_address shows up, but how do i link this parameter to the column called base in the system contents tab? I am guessing this is the same parameter?

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4 Replies
AnandRaj_S_Intel
Employee
137 Views

Hi,

 

  1. VHDL Generics is not used for base address under system contents tab.
  2. VHDL GenericsVHDL allows the designer to parametrize the entity during the component instantiation.

As you add the components in the Qsys/platform designer system, you specify their base addresses within the span of the address space using Qsys GUI.

Base address can be directly edited by the user, or it can be assigned automatically by using the Assign Base Addresses from System menu

 

We can control on the offset address using HDL.

 

Refer below link

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/qts/qsys_components.pdf

ftp://ftp.intel.com/Pub/fpgaup/pub/Intel_Material/13.1/Tutorials/Making_Qsys_Components.pdf

 

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

 

Regards

Anand

OKris1
Beginner
137 Views

Hi Anand My custom VHDL code is a basic 2's complement calculator (which for the moment only do multiplication) It has AVALON MM slave interface with 3 registers which are two for input value and one output register for multiplication result When I set a generic value called base_address the first register is given this address, and the second is given base_address+1 and the next one is given base_address+2 I am ot sure if I understand the base column in QSYS system contents tab, but I thought this was the same thing = base_address? When I use Assign Base address from system menu all my QSYS components are given a sequenctially logic address span that do not conflict, but I dont understand how my CUSTOM MADE qsys COMPONENT addressable registers are related to the BASE value in QSYS system contents? Br Øystein ------ Original Melding ------ Fra: "Intel Forums" <supportreplies@intel.com> Til: "oystein.kristiansen@embida.no" <oystein.kristiansen@embida.no> Sendt: 29.05.2019 04.15.07 Emne: AnandRS answered you: How to set QSYS component base address through VHDL generics
AnandRaj_S_Intel
Employee
137 Views

NO,

Let me explain with example:

  1. Let us say we have a 2 custom component namely A & B.
  2. The Qsys system assign the base address & address span for the component.(A=0x0000 b =0x000F)  base of A=0x0000 b=0x000F and address span for component A=0x000 to 0x000E.
  3. In component A hdl we have a case statement when "01" => Z <= X; 01 is address =offset address.Now data is stored in base address of the component + offset address =0x0001.

 

To have better understanding go through course like Using the Nios II Processor: Hardware Development,Using the Nios II Processor: Software Development & Using the Nios II Processor: Custom Components and Instructions

https://www.intel.com/content/www/us/en/programmable/support/training/catalog.html

 

Regards

ANAND

sstrell
Honored Contributor II
137 Views

No, the base address column in Platform Designer is the base address of your component as seen from a master connected to your slave. Addresses you set up in your custom component are offsets of this. Remember, every master in the system has its own unique address map. So if you set a base address of, say, 0x1000, in the Platform Designer Base address column, the first register (word) in your component would be accessed by the master at address 0x1000. Depending on the data bus width, the next register (again, word) would be accessed at 0x1002 (for 16-bit data) or 0x1004 (for 32-bit data). The master addressing is byte-wide, which is why I increased by 2 or 4. The slave-side addressing is word-based.

 

Any generics you use in your custom component code can be optionally customized in the parameter editor when your component is added to the system, but addressing of master-accessible registers in the custom component is not a good idea (or it might even be illegal, not sure). The address map for your component must be fixed at generation time (the End address column in Platform Designer is set by this).

 

See this online training for all details about creating custom components and their addressing:

 

https://www.intel.com/content/www/us/en/programmable/support/training/course/oqsys3000.html

 

#iwork4intel

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