How to time constrain an combinational loop on FPGA?

[BStui2]

Hi,

I am trying to time constrain a combinational loop.

I need a free running oscillator which I can coarsly tune and enable.

Unfortunately commands like:

set_net_delay

set_min_delay

set_max_delay

are ignored because these relate to a clock, which is not present.

With the Vivado tools I can effectively specify a combinational delay to get a single NAND gate to oscillate roughly at a frequency of 100MHz when enabled. Vivado will simply route the signal via a winding path that comes close to the 10 ns delay I have specified.

How can I do this with Quartus Prime Pro?

Thanks!

[sstrell]

I'm not sure why you think those SDC commands are clock path specific. They should work on any path. set_min|max_delay overrides any other constraints on a path (other than set_false_path).

#iwork4intel

[BStui2]

There are 3 reasons why I think this is the case:

1) SDC and TimeQuest API Reference Manual (this is from Quartus II, I was unable to find this manual for Quartus Prime pro)

Page 2-35

set_max_delay

DescriptionSpecifies a maximum delay exception for a given path.The maximum delay is similar to changing the setup relationship (latching clock edge - launching clock edge), except that it can be applied to input or output ports without input or output delays assigned to them. Maximum delays are always relative to any clock network delays (if the source or destination is a register) or any input or output delays (if the source or destination is a port). Therefore, input delays and clock latencies are added to the data arrival times. Clock latencies also added to data required times and output delays are subtracted from data required times.

In practice:

2) Although applying set_min_timing delay and set_max_timining delay in the timing analyzer does not return any errors or warnings, when performing final timing analysis the paths that I assignd constraints to can not be found. Note: these are still visible in the post P&R netlist!

3) Using signal tap I can observer that no matter how I constrain paths, these paths do not fit the constraint at all. And worse, with each new build the behaviour is different.

I hope this proves my case, can you help me find a solution?

[KhaiChein_Y_Intel]

Hi,

Could you share a simple test case for error replication?

Thanks.

Best regards,

KhaiY

[BStui2]

Hi, there were some hollidays here so I couldn't reply sooner.

I have attached a minimal test case which shows a net delay is applied for enable_i to nand_ro~1, but is not applied to the loopback nand-ro~1 to nand_ro~1.

I sure hope this helps!

[KhaiChein_Y_Intel]

Hi,

Upon checking, setting the net delay of a combinational loop is currently unsupported in the software.

Thanks.

Best regards,

KhaiY

[KhaiChein_Y_Intel]

Hi,

Do you have any updates?

Thanks.

Best regards,

KhaiY

[AEsqu]

Hi KhaiY,

I was wondering why you ask him an update while said before that quartus does not support it.

Maybe he wen't back to Xilinx

[KhaiChein_Y_Intel]

Hi AEsqu,

Just to check with BStui2 if there is any other questions before I transition this thread to community support. 

Since there is no other question, I will transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

Best regards,

KhaiY