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UserQuartus19-3
Beginner
289 Views

Ignoring clock skews in set_max_delay constraint

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Hi 

I have a clock domain crossing in my design  and I have placed synchronisers at the crossing paths. I have specified the constraint set_max_delay -from [src clk] -to [dest_clk] [time period of src clk] for avoiding timing errors on the crossing paths. 

However Quartus is throwing timing errors with huge clock skews between the 2 clocks. I wanted to know how we can specify to ignore the clock path skews in such a scenario. 

I have seen related discussions (https://community.intel.com/t5/Programmable-Devices/set-max-delay-vs-set-net-delay/td-p/232670) but couldn't understand any solution out of it. 

I am using Arria 10 FPGA and Quartus 19.3 Prime Pro Version.

 

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1 Solution
sstrell
Honored Contributor II
236 Views

Without looking at your design, if these clock domains are asynchronous, you should use set_clock_groups to simply cut all paths between them.  By using set_max[min]_delay, the tool will still analyze timing on paths that go between these clock domains and you see what's happening.

So simply try this instead of set_max[min]_delay:

set_clock_groups -asynchronous -group src_clock -group dest_clk

If the clock domains are synchronous to each other and you're still getting timing failures, then you may need to look into using multicycles or, better yet, adding registers or using a FIFO to handle the clock crossings.

#iwork4intel

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6 Replies
254 Views

Hi,

Can you share the design.qar for investigation?

Thanks.

Best regards,

KhaiY

UserQuartus19-3
Beginner
248 Views

Hi KhaiY

Please find attached .

sstrell
Honored Contributor II
237 Views

Without looking at your design, if these clock domains are asynchronous, you should use set_clock_groups to simply cut all paths between them.  By using set_max[min]_delay, the tool will still analyze timing on paths that go between these clock domains and you see what's happening.

So simply try this instead of set_max[min]_delay:

set_clock_groups -asynchronous -group src_clock -group dest_clk

If the clock domains are synchronous to each other and you're still getting timing failures, then you may need to look into using multicycles or, better yet, adding registers or using a FIFO to handle the clock crossings.

#iwork4intel

View solution in original post

216 Views

Hi,


Have you tried Sstrell's suggestions?


Thanks.

Best regards,

KhaiY


UserQuartus19-3
Beginner
207 Views

Yes KhaiY I've cleaned timing using Sstrell's suggestions and my sof file works correctly.

Thanks.  

199 Views

Hi,

 

Thanks for your updates. I will now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you

Best regards,

KhaiY

 

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