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Instantiating VHDL entities into a Verilog top level

Altera_Forum
Honored Contributor II
‎02-01-2017 07:27 PM
1,398 Views

I would like to instantiate some VHDL entities into A Verilog top level. 

Any ides on how to do this?
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Altera_Forum
Honored Contributor II
‎02-01-2017 08:57 PM
700 Views

You don't have to do anything special. Just map the ports in your Verilog instantiation as usual.

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Altera_Forum
Honored Contributor II
‎02-02-2017 01:51 PM
700 Views

Thanks, that did it.

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