Hi,
I use a package in my Project to define some constants. I use some constant integers to access array cells.
It works in vhdl files but not in the top level entity which is a graphic file (bdf).
example:
-- declared in the package:
type INT_REG_TYPE is array (0 to 255) of std_logic_vector(15 downto 0);
constant VIDEO_REG : integer := 10;
-- declared in vhdl files:
internal_regs : out INT_REG_TYPE;
internal_regs(VIDEO_REG) <= x"1234";
-- BDF
I would like to use package constants to map signals in the graphic file as I do in vhdl file.
I try to add some VHDL statements in the top_entity.bdf file properties but it does not work.
LIBRARY WORK;
USE WORK.CST_PACKAGE.ALL;
Is it possible to access a package within a bdf file ? How should I do that ?
Thanks.
