Is anybody else completely dissatisfied with this new forum?

[GLees]

This used to be a robust forum, lots of new questions everyday and, most impotantly, lots of responses. This new forum is clunky and time consuming to navigate. Nobody seems interested anymore. I used to check-in everyday to see what's new. Not any more.

[MaryT_Intel]

Hi, What do you mean you have to 'unfold a lot of stuff'? We're trying to improve the site so I'm interested in hearing any issues you may be experiencing so we can fix them. Thanks,

Mary T.

Community Manager

[corestar]

Well, if it's any consolation, the "modernized" Xilinx forums introduced a week or so ago makes the Altera forums look like the work of genius.

Well designed support forums has ceased to be a possible reason to move back to Xilinx.

[MFaiz]

HI, I agree wih Gleez. The previous forum was engaging, in the new Forum it feels like I am lost. Earlier I used to just all the questions posted wrt OpenCL everyday. Now I hardly check the forums, as it is not sub categorized properly.

Earlier Forums were more engaging and used to get response very fast. Now most of the questions go unanswered or get response weeks of posting the question.

Hope this will be taken positively by Intel, to improve there customer engagement.

[HRZ]

A new version of the forum was promised to be unveiled in November/December time frame with many improvements including better categorization. I guess we will have to wait until the new version is released.

[CV1]

I hate this, i cant find anything, im in tears.

What was wrong with the old one?

Were users complaining?

Since users and helpers arent being paid, here by their good graces, WHY make it harder for them?

[corestar]

Good grief, I did not think Intel could make the forums worse, but I was wrong! Has anyone in the group that designs these forums ever actually used a forum? Do you do any testing at all?

When you go to the main FPGA forum, you can no longer right-click on a sub forum and open it in a new tab (tried FireFox and IE). This was a nice way to get back to the main forum page when done. Ok, I'll just have to hit back a few times. NOPE! When you hit back, it takes you to the main Intel community and not the FPGA forums.

You still have the "More Answers" and "View More" ....

[HRZ]

I finally got access to the forum again since my access was broken after the update... Indeed not much has been improved in the promised update. The only step forward that I can see is that posts now fill the horizontal space. A couple notes:

• As corestar mentioned, "More Answers" and "View More" are back even though they were already removed in the previous version.
• Topics are still sorted by "Latest post" instead of "Most recent activity" by default. Furthermore, the time written under the post title still shows the time of first reply rather than the last.
• Subcategories were not introduced for the large FPGA sections.
• The editor is heavily borked. Backspace and Delete keys remove two characters at a time in most cases. Enter also adds two new lines. CTRL + Z (undo) acts erratically and removes too much text at a time. CTRL + Y (redo) does not even work. Submitting replies takes A LONG time. I had to write this reply in a text editor and copy/paste it into the forum since it is nearly impossible to write more than one line with the current editor.
• The "Search the community or Ask a Question" bar obstructs half of the screen when you reach the end of a topic.

These are likely not the only problems since I have used the forum for only a couple of minutes.

[sstrell]

• "Topics are still sorted by "Latest post" instead of "Most recent activity" by default. Furthermore, the time written under the post title still shows the time of first reply rather than the last.

@HRZ, this is not my experience. As long as I'm logged in, the default is "Most recent activity," as it should be. If I'm not logged in, it's set to "Latest post".

[HRZ]

You are correct. I just checked again and the default is "Most recent activity" after I log in. I guess the forum admins should also change the default value for when the user is not logged in to keep things consistent.

[MaryT_Intel]

You're right, that should not happen. Thanks for noting it. I'll take it back to our team to address.

Also, the FPGA team is still working on creating those sub categories everyone's been asking about. They're in process now and we expect them to go live in January for you.

Thanks for everyone feedback and input, we appreciate it.

Mary T.

Community Manager

[Pvand1]

Well I can't sleep and have exausted my other go-to's and decided to give it another try. My biggest issues, apart from the previously mentioned is the total lack of mobile browser compatibility. All I see on my 10" tablet is a big blue bar wit an intel logo and some links, another big blue bar with community and my account number (that now I seem to be able to edit but there is no save button) and below that a search bar. Ah, if I scroll the searchbar disappears and I can now see the lines :). It would be really great to see thhe texts full-width, or at least twice the current size. Apart from my keyboard my screen is showing mabe 10% interesting stuff. i.e. this textbox.

Also I dislike the js void links on the first page. If I just browse the forum to see if I can help someone out I would like to visit that page and then open the 8 links in separate tabs (or have a recent posts page with all of them) instead of going back to the first page. Each time and clicking trough the links. But I seem to remember chatting about this stuff with a research group, did none of that feedback make it trough?

When me and my collegues were complaining about Xilinx' documentation and forum I used to suggest using Intel/Altera partially because of the good forum support, searching wasn't always easy, but it was easier to use than this. I've stopped suggesting Intel now. I propose Lattice instead.

[Edit] Now I know why the void links are there, more than 4 tabs crashes the browser. Positive thing: this edit box is exactly what I wanted when I said the stuff about screen utilization. But where is the save button here? Found it, I just needed to rotate into portrait orientation...[/edit]

[CV1]

Another problem is that the threads no longer show as closed. I can see a Best Answer but that itself shouldnt mean no further replies should be posted. Previously, the thread showed Locked at the bottom. Not seeing that, I posted three times today only to have the posted rejected because its only then that you find out its locked.

[HRZ]

Great point mentioned by the above user (whose name seems to be garbled for some reason). Indeed this is another regression after the update that now, all the "links" on the sections show up as "javascrip:void(0);", making it impossible to open multiple threads in parallel in different tabs. I had encountered this issue also before the update, but that was only when I did not wait long enough for the page to load completely.

Another thing to mention is that the forum really needs a proper “quote” feature; or maybe there is one but I cannot find it. The new tree-based replying could be considered as replacement for quoting, but it has a big disadvantage which is the fact that it breaks the order of the posts; i.e. if someone makes post A and someone else makes post B after it and then someone else replies to post A directly, the reply will end up before post B even though it was made later. In a big active thread, this is going to make it very difficult to tell which post is new and which is old.

[Pvand1]

like I wrote before I missed recent post, but I found something like it: on https://forums.intel.com/s/ and then click the all discussions, but it would be nice to have this for FPGAs only and not for ALL Intel products.

As to my garbled nickname I cannot change it to anything that resembles the nickname I had on the Alteraforum (pietervanderstar).

[Pvand1]

It would also be nice to have support for Verilog and VHDL in the code markup. Now only a few of the keywords are recognised, while sometimes the Verilog ' operator (or whatever the proper name is) sometimes gets mistaken for start of string/comment as all text after is green.

[Pvand1]

I thought a bit more about this, and Intel has more than just VHDL and Verilog on the fora. Maybe user selectable, when autodetect does not work, so the poster can select the language for markup might aid readibility.

[Pvand1]

Just got a new issue, the view more button disappeared, which means I cannot view the last post in longer threads (such as this one).

[MaryT_Intel]

Hi @Pvand1​ ,

Regarding: the view more button disappearing on you, can you let me know which browser you're using?

In the meantime, from inside the very first post, you can select 'Go To Latest Reply". Does that help?

Let us know on that browser so we can investigate for you. Thank you,

Mary T.

Community Manager

[Pvand1]

I saw the go to last after I posted my message, but the edit page did not load correctly. So I could not update. I actually prefer the go to last.

My browser is Firefox 63 on android 8.

[ECD2]

I would like to add my agreement with all of the above posts.

This design is a major step backward. Intel, it is your intent to drive users from this forum? If so, this design will do it!!!!

This forum design = Windows 8. And we all know how that turned out!

[corestar]

@HazlinaR_Intel​ ,

Well, here is goes with random code off the internet:

---------------------------------------------------------------------- -- GCD CALCULATOR (ESD book figure 2.11) -- Weijun Zhang, 04/2001 -- -- we can put all the components in one document(gcd2.vhd) -- or put them in separate files -- this is the example of RT level modeling (FSM + DataPath) -- the code is synthesized by Synopsys design compiler ----------------------------------------------------------------------   -- Component: MULTIPLEXOR --------------------------------------------   library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all;   entity mux is port( rst, sLine: in std_logic; load, result: in std_logic_vector( 3 downto 0 ); output: out std_logic_vector( 3 downto 0 ) ); end mux;   architecture mux_arc of mux is begin process( rst, sLine, load, result ) begin if( rst = '1' ) then output <= "0000"; -- do nothing elsif sLine = '0' then output <= load; -- load inputs else output <= result; -- load results end if; end process; end mux_arc; -- Component: COMPARATOR ---------------------------------------------   library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all;   entity comparator is port( rst: in std_logic; x, y: in std_logic_vector( 3 downto 0 ); output: out std_logic_vector( 1 downto 0 ) ); end comparator;   architecture comparator_arc of comparator is begin process( x, y, rst ) begin if( rst = '1' ) then output <= "00"; -- do nothing elsif( x > y ) then output <= "10"; -- if x greater elsif( x < y ) then output <= "01"; -- if y greater else output <= "11"; -- if equivalance. end if; end process; end comparator_arc;   -- Component: SUBTRACTOR ----------------------------------------------   library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all;   entity subtractor is port( rst: in std_logic; cmd: in std_logic_vector( 1 downto 0 ); x, y: in std_logic_vector( 3 downto 0 ); xout, yout: out std_logic_vector( 3 downto 0 ) ); end subtractor;   architecture subtractor_arc of subtractor is begin process( rst, cmd, x, y ) begin if( rst = '1' or cmd = "00" ) then -- not active. xout <= "0000"; yout <= "0000"; elsif( cmd = "10" ) then -- x is greater xout <= ( x - y ); yout <= y; elsif( cmd = "01" ) then -- y is greater xout <= x; yout <= ( y - x ); else xout <= x; -- x and y are equal yout <= y; end if; end process; end subtractor_arc;   -- Component: REGISTER ---------------------------------------------------   library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all;   entity regis is port( rst, clk, load: in std_logic; input: in std_logic_vector( 3 downto 0 ); output: out std_logic_vector( 3 downto 0 ) ); end regis;   architecture regis_arc of regis is begin process( rst, clk, load, input ) begin if( rst = '1' ) then output <= "0000"; elsif( clk'event and clk = '1') then if( load = '1' ) then output <= input; end if; end if; end process; end regis_arc;   -- component: FSM controller --------------------------------------------   library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all;   entity fsm is port( rst, clk, proceed: in std_logic; comparison: in std_logic_vector( 1 downto 0 ); enable, xsel, ysel, xld, yld: out std_logic ); end fsm;   architecture fsm_arc of fsm is   type states is ( init, s0, s1, s2, s3, s4, s5 ); signal nState, cState: states;   begin process( rst, clk ) begin if( rst = '1' ) then cState <= init; elsif( clk'event and clk = '1' ) then cState <= nState; end if; end process;   process( proceed, comparison, cState ) begin case cState is when init => if( proceed = '0' ) then nState <= init; else nState <= s0; end if; when s0 => enable <= '0'; xsel <= '0'; ysel <= '0'; xld <= '0'; yld <= '0'; nState <= s1; when s1 => enable <= '0'; xsel <= '0'; ysel <= '0'; xld <= '1'; yld <= '1'; nState <= s2; when s2 => xld <= '0'; yld <= '0'; if( comparison = "10" ) then nState <= s3; elsif( comparison = "01" ) then nState <= s4; elsif( comparison = "11" ) then nState <= s5; end if; when s3 => enable <= '0'; xsel <= '1'; ysel <= '0'; xld <= '1'; yld <= '0'; nState <= s2; when s4 => enable <= '0'; xsel <= '0'; ysel <= '1'; xld <= '0'; yld <= '1'; nState <= s2;   when s5 => enable <= '1'; xsel <= '1'; ysel <= '1'; xld <= '1'; yld <= '1'; nState <= s0; when others => nState <= s0; end case; end process; end fsm_arc;   ---------------------------------------------------------------------- -- GCD Calculator: top level design using structural modeling -- FSM + Datapath (mux, registers, subtracter and comparator) ----------------------------------------------------------------------   library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; use work.all;   entity gcd is port( rst, clk, go_i: in std_logic; x_i, y_i: in std_logic_vector( 3 downto 0 ); d_o: out std_logic_vector( 3 downto 0 ) ); end gcd;   architecture gcd_arc of gcd is   component fsm is port( rst, clk, proceed: in std_logic; comparison: in std_logic_vector( 1 downto 0 ); enable, xsel, ysel, xld, yld: out std_logic ); end component;   component mux is port( rst, sLine: in std_logic; load, result: in std_logic_vector( 3 downto 0 ); output: out std_logic_vector( 3 downto 0 ) ); end component;   component comparator is port( rst: in std_logic; x, y: in std_logic_vector( 3 downto 0 ); output: out std_logic_vector( 1 downto 0 ) ); end component;   component subtractor is port( rst: in std_logic; cmd: in std_logic_vector( 1 downto 0 ); x, y: in std_logic_vector( 3 downto 0 ); xout, yout: out std_logic_vector( 3 downto 0 ) ); end component;   component regis is port( rst, clk, load: in std_logic; input: in std_logic_vector( 3 downto 0 ); output: out std_logic_vector( 3 downto 0 ) ); end component;   signal xld, yld, xsel, ysel, enable: std_logic; signal comparison: std_logic_vector( 1 downto 0 ); signal result: std_logic_vector( 3 downto 0 );   signal xsub, ysub, xmux, ymux, xreg, yreg: std_logic_vector( 3 downto 0 );   begin   -- doing structure modeling here   -- FSM controller TOFSM: fsm port map( rst, clk, go_i, comparison, enable, xsel, ysel, xld, yld ); -- Datapath X_MUX: mux port map( rst, xsel, x_i, xsub, xmux ); Y_MUX: mux port map( rst, ysel, y_i, ysub, ymux ); X_REG: regis port map( rst, clk, xld, xmux, xreg ); Y_REG: regis port map( rst, clk, yld, ymux, yreg ); U_COMP: comparator port map( rst, xreg, yreg, comparison ); X_SUB: subtractor port map( rst, comparison, xreg, yreg, xsub, ysub ); OUT_REG: regis port map( rst, clk, enable, xsub, result ); d_o <= result;   end gcd_arc;   ---------------------------------------------------------------------------