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GLees
New Contributor I
9,404 Views

Is anybody else completely dissatisfied with this new forum?

This used to be a robust forum, lots of new questions everyday and, most impotantly, lots of responses. This new forum is clunky and time consuming to navigate. Nobody seems interested anymore. I used to check-in everyday to see what's new. Not any more.

112 Replies
ECD2
Beginner
207 Views

I would like to add my agreement with all of the above posts.

This design is a major step backward. Intel, it is your intent to drive users from this forum? If so, this design will do it!!!!

 

This forum design = Windows 8. And we all know how that turned out!

 

 

corestar
New Contributor I
207 Views

@HazlinaR_Intel​ ,

 

Well, here is goes with random code off the internet:

 

 

---------------------------------------------------------------------- -- GCD CALCULATOR (ESD book figure 2.11) -- Weijun Zhang, 04/2001 -- -- we can put all the components in one document(gcd2.vhd) -- or put them in separate files -- this is the example of RT level modeling (FSM + DataPath) -- the code is synthesized by Synopsys design compiler ----------------------------------------------------------------------   -- Component: MULTIPLEXOR --------------------------------------------   library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all;   entity mux is port( rst, sLine: in std_logic; load, result: in std_logic_vector( 3 downto 0 ); output: out std_logic_vector( 3 downto 0 ) ); end mux;   architecture mux_arc of mux is begin process( rst, sLine, load, result ) begin if( rst = '1' ) then output <= "0000"; -- do nothing elsif sLine = '0' then output <= load; -- load inputs else output <= result; -- load results end if; end process; end mux_arc; -- Component: COMPARATOR ---------------------------------------------   library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all;   entity comparator is port( rst: in std_logic; x, y: in std_logic_vector( 3 downto 0 ); output: out std_logic_vector( 1 downto 0 ) ); end comparator;   architecture comparator_arc of comparator is begin process( x, y, rst ) begin if( rst = '1' ) then output <= "00"; -- do nothing elsif( x > y ) then output <= "10"; -- if x greater elsif( x < y ) then output <= "01"; -- if y greater else output <= "11"; -- if equivalance. end if; end process; end comparator_arc;   -- Component: SUBTRACTOR ----------------------------------------------   library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all;   entity subtractor is port( rst: in std_logic; cmd: in std_logic_vector( 1 downto 0 ); x, y: in std_logic_vector( 3 downto 0 ); xout, yout: out std_logic_vector( 3 downto 0 ) ); end subtractor;   architecture subtractor_arc of subtractor is begin process( rst, cmd, x, y ) begin if( rst = '1' or cmd = "00" ) then -- not active. xout <= "0000"; yout <= "0000"; elsif( cmd = "10" ) then -- x is greater xout <= ( x - y ); yout <= y; elsif( cmd = "01" ) then -- y is greater xout <= x; yout <= ( y - x ); else xout <= x; -- x and y are equal yout <= y; end if; end process; end subtractor_arc;   -- Component: REGISTER ---------------------------------------------------   library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all;   entity regis is port( rst, clk, load: in std_logic; input: in std_logic_vector( 3 downto 0 ); output: out std_logic_vector( 3 downto 0 ) ); end regis;   architecture regis_arc of regis is begin process( rst, clk, load, input ) begin if( rst = '1' ) then output <= "0000"; elsif( clk'event and clk = '1') then if( load = '1' ) then output <= input; end if; end if; end process; end regis_arc;   -- component: FSM controller --------------------------------------------   library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all;   entity fsm is port( rst, clk, proceed: in std_logic; comparison: in std_logic_vector( 1 downto 0 ); enable, xsel, ysel, xld, yld: out std_logic ); end fsm;   architecture fsm_arc of fsm is   type states is ( init, s0, s1, s2, s3, s4, s5 ); signal nState, cState: states;   begin process( rst, clk ) begin if( rst = '1' ) then cState <= init; elsif( clk'event and clk = '1' ) then cState <= nState; end if; end process;   process( proceed, comparison, cState ) begin case cState is when init => if( proceed = '0' ) then nState <= init; else nState <= s0; end if; when s0 => enable <= '0'; xsel <= '0'; ysel <= '0'; xld <= '0'; yld <= '0'; nState <= s1; when s1 => enable <= '0'; xsel <= '0'; ysel <= '0'; xld <= '1'; yld <= '1'; nState <= s2; when s2 => xld <= '0'; yld <= '0'; if( comparison = "10" ) then nState <= s3; elsif( comparison = "01" ) then nState <= s4; elsif( comparison = "11" ) then nState <= s5; end if; when s3 => enable <= '0'; xsel <= '1'; ysel <= '0'; xld <= '1'; yld <= '0'; nState <= s2; when s4 => enable <= '0'; xsel <= '0'; ysel <= '1'; xld <= '0'; yld <= '1'; nState <= s2;   when s5 => enable <= '1'; xsel <= '1'; ysel <= '1'; xld <= '1'; yld <= '1'; nState <= s0; when others => nState <= s0; end case; end process; end fsm_arc;   ---------------------------------------------------------------------- -- GCD Calculator: top level design using structural modeling -- FSM + Datapath (mux, registers, subtracter and comparator) ----------------------------------------------------------------------   library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; use work.all;   entity gcd is port( rst, clk, go_i: in std_logic; x_i, y_i: in std_logic_vector( 3 downto 0 ); d_o: out std_logic_vector( 3 downto 0 ) ); end gcd;   architecture gcd_arc of gcd is   component fsm is port( rst, clk, proceed: in std_logic; comparison: in std_logic_vector( 1 downto 0 ); enable, xsel, ysel, xld, yld: out std_logic ); end component;   component mux is port( rst, sLine: in std_logic; load, result: in std_logic_vector( 3 downto 0 ); output: out std_logic_vector( 3 downto 0 ) ); end component;   component comparator is port( rst: in std_logic; x, y: in std_logic_vector( 3 downto 0 ); output: out std_logic_vector( 1 downto 0 ) ); end component;   component subtractor is port( rst: in std_logic; cmd: in std_logic_vector( 1 downto 0 ); x, y: in std_logic_vector( 3 downto 0 ); xout, yout: out std_logic_vector( 3 downto 0 ) ); end component;   component regis is port( rst, clk, load: in std_logic; input: in std_logic_vector( 3 downto 0 ); output: out std_logic_vector( 3 downto 0 ) ); end component;   signal xld, yld, xsel, ysel, enable: std_logic; signal comparison: std_logic_vector( 1 downto 0 ); signal result: std_logic_vector( 3 downto 0 );   signal xsub, ysub, xmux, ymux, xreg, yreg: std_logic_vector( 3 downto 0 );   begin   -- doing structure modeling here   -- FSM controller TOFSM: fsm port map( rst, clk, go_i, comparison, enable, xsel, ysel, xld, yld ); -- Datapath X_MUX: mux port map( rst, xsel, x_i, xsub, xmux ); Y_MUX: mux port map( rst, ysel, y_i, ysub, ymux ); X_REG: regis port map( rst, clk, xld, xmux, xreg ); Y_REG: regis port map( rst, clk, yld, ymux, yreg ); U_COMP: comparator port map( rst, xreg, yreg, comparison ); X_SUB: subtractor port map( rst, comparison, xreg, yreg, xsub, ysub ); OUT_REG: regis port map( rst, clk, enable, xsub, result ); d_o <= result;   end gcd_arc;   ---------------------------------------------------------------------------

 

 

corestar
New Contributor I
207 Views

@NRaml, looks like code insert is still broken to me. On my system (Windows 7 and FireFox or IE) it shows all 306 lines with no scrollbar.

HRZ
Valued Contributor II
207 Views

Same here, completely expanded by default and no scrollabr.

Pvand1
Novice
207 Views

I saw the go to last after I posted my message, but the edit page did not load correctly. So I could not update. I actually prefer the go to last.

My browser is Firefox 63 on android 8.

Pvand1
Novice
207 Views

ff63 android 8 same thing, no scrollbar. But I think i prefer it this way. Maybe 300+ lines is a bit too much, this might be something where view more functionality might be useful. Default only showa few lines and then have a button/link to toggle showing the complete thing.

Pvand1
Novice
207 Views

I thought a bit more about this, and Intel has more than just VHDL and Verilog on the fora. Maybe user selectable, when autodetect does not work, so the poster can select the language for markup might aid readibility.

Pvand1
Novice
207 Views

Just got a problem where links to a thread actually open another, or loading takes >20 seconds. Also got a script problem:IMG_20181229_180140.jpg

Saw my username got improved by Intel, so that is a bit better.

208 Views

Hello,

 

We need the following information in order to troubleshoot this further.

 

  1. Browser type along with the version number that you are using
  2. Have you  been able to reproduce this problem multiple times?

 

thanks

Raman Kuppuswamy

Pvand1
Novice
208 Views

Sure, for me it still is:

https://forums.intel.com/s/question/0D70P000006ALx4SAG

ff63 on android8

rockstarrocks
Novice
209 Views

Site looks great to be honest but there are issues too. There are so many threads here unanswered, seems like no one cares. Plus I hate the never ending scroll to get the last post in a thread. I would prefer a pages approach i.e. thread divided into several pages with each post getting their #, so it's easier to reference back.

GLees
New Contributor I
210 Views

Since I started this thread about four months ago I feel it's appropriate for me to weigh in again. I'm really happy with the changes that have been made. The forum is back to being "pretty easy to use and navigate" and I see more activity now. Thanks for all the hard work.

schendel_nsf
Novice
211 Views

Thanks for your post !

 

After the promised update disappointed, I had all but given up on it, but you are right, the forum has become usable again.

 

In particular, for those who say the design offers nothing better:

Have you noticed that you can (now) check and write answers on your tablet/smart phone ?

That would not have worked well with the old one (and also not with the current design some time ago).

 

Please keep listening to requests from the top posters / moderators of the Altera Forum, and Keep up the good work !

MaryT_Intel
Community Manager
212 Views

Hi @rockstarrocks​ , We did fix the scroll to get to the last post in a thread. On the very first post in the thread, there is a "Go to latest reply" that should help. I agree that having each post getting a # is great, we'll keep looking at improvement options so we appreciate your input. Thank you!

Mary T.

Community Manager

HRZ
Valued Contributor II
212 Views

Big step forward with addition of sub-sections for the large sections.

 

Though I think something should be done about the "Application Acceleration With FPGAs" section, since many of the questions posted there are OpenCL-related questions from people who just happen to be using Intel PAC.

mfro
New Contributor I
212 Views

Agreed. Noticeable improvement.

 

Now - with the integration of all the other Intel forums - I'm missing a functionality to navigate 'upwards' from a forum.

 

Before, I was just clicking on 'Community' that brings you to the top level and clicked my way down again from there. Since there are a lot more forums on the way down now, this has become way more awkward than before.

Daixiwen
New Contributor I
212 Views

Yes it is going better, but it is still slow in some cases. On this thread (with 95 messages), clicking on the "Go to latest reply" takes more than one minute before the end of the thread is displayed on my computer. And Firefox complained twice that a script on the page was taking too much time to process.

 

Another feature that is still missing imho is a read/unread status. When I come to the forum I'd like to know which thread has messages I haven't read, and in each thread to jump to the first unread message. Without this each time I come to the forum I have to guess from the approximate date and time I was on the forum last time. And even like this it isn't easy, because the thread list still shows the date and time of the first post in a thread instead of the last one.

 

Something rather annoying also happened to me today. I was writing a (long) answer and when clicking on the "Answer" button, I got the message "This thread/question has been closed. It has a best answer selected!". So two questions:

 1) the selected "best answer" is not visible on the thread itself. In the thread list I can see that the question has been answered, but there is no indication once we are in the thread itself.

 2) why is the "write an answer" box still present on the page if it is not possible to answer?

 

But keep up the good work, it's a step in the right direction!

Daixiwen
New Contributor I
212 Views

Just a short update... posting my answer just here above took 88 seconds. And Firefox complained about the javascript taking too much time 5 times.

GLees
New Contributor I
212 Views

Yes, not having "read/unread" status is still a major nuisance for me.

EGrub
Beginner
212 Views

It is very slow and often tells me I should check my internet connection. But my connection is good, no issues with other web pages.

Editor seems to be buggy.

More than 10000 posts under Quartus, no further categories.

I couldn't find a place to report bugs.

Search is not good.

No possibility to get direct support like it was with the Altera service requests.

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