Issues debugging DDR3 controller using SignalTap on Quartus Prime Standard 23.1 with Arria V GZ FPGA

[JuanEscobedo]

Hello,

I have a simple design where a state machine writes synthetic data to DDR using the Avalon bus of the DDR3 controller and reads it back after some time, processes it, and writes new data to DDR.

The state machine and all the logic is driven by the afi_clk PLL output of the IP.

The issue I am encountering is when trying to add all the AVL signals to signal tap, I can only see the ones driven by the logic and all the signals coming from the IP either pre-synthesis or post-fitting, are missing.

I have added the pragmas keep and preserve to avoid the compiler from optimizing them away or merging them. I have also registered the outputs and neither the original signal nor the registered ones show up on the SignalTap signal selector. 

What is weirder is I can see the signals driven by the logic advancing in the state machine as expected (minus being clocked by the wrong clock since I cannot see the output clock of the IP).

Any help would be appreciated.

[sstrell]

Can you clarify better what signals you can and cannot see?  You say you "see the ones driven by the logic", but you can't see "the signals coming from the IP"?  It's not clear what you mean by this.  Like you can see the address bits (signals from logic to IP) but not readdata from the IP?

If you are talking about the memory signals that go out to the external memory, you can't tap those signals assuming you are using the hard controller.

[JuanEscobedo]

Hello. Yes, I am using the hard controller.

My issue is the the avalon bus signals that are outputs of the IP. Namely, readdata, datavalid, and ready. They do not show up in signaltap neither presynthesis nor post fitting. Signals used as input to the controller which are driven by RTL show up fine.

[sstrell]

ready is not an Avalon signal.  Do you mean waitrequest?

Can you show your design instantiation or design in Platform Designer and screenshots of what you're seeing when you try to tap the nodes in Signal Tap?  If you're leaving signals unconnected, they may have been optimized away.

[JuanEscobedo]

Hello,

I have attached the source RTL of my top level design and the top level RTL of the DDR3 controller generated by the wizard for your reference.

As you can see, avl_ready is indeed one of the ports of the avl interface for the DDR3 controller.

Below are the screenshots of the signals that show in post-fitting and pre-synthesis:

[JuanEscobedo]

Oh and to reiterate, I also cannot use the afi_clk output as the signaltap clock even though the state machine is driven by it and I see the state variable as well as the signals driven by the logic (addr, write data, write req, read req) toggle so it must be present and driving logic.

[sstrell]

I forgot that some IP call the waitrequest signal "ready" for some reason.  The official name is waitrequest.

Does turning on "Include subentities" in the Node Finder do anything?

Check that the missing signals exist in the RTL Viewer and Technology Map Viewers.  If they show up there but not in the Node Finder, something strange is going on.

[JuanEscobedo]

Hello!

A little bit of progress. I changed the state machine logic a little bit and now I can see the ready, data valid, and read data signals ( at least the registered version) so it seems it was indeed a problem of the logic was being optimized away. I have attached the latest version of my code for reference.

However, I still cannot add the afi_clk as the SignalTap instance. Using the RTL viewer I can confirm all 4 output signals from the controller are present:

And using the technology map viewer I can also confirm the missing signal (afi_clk) is present

Enabling "Include Sub entities" on SignalTap shows the ddr3 controller instance if trying to view the top level, but still, the clock signal is not found:

For completeness, here is a screenshot of the SignalTap instance running. You will see something is happening and in somewhat the right sequence, however, I am sampling using the system_clk which is 50MHz, and not the avl_clk which is 125MHz

[sstrell]

Have you tried searching on "afi_clk" instead of "avl_clk"?  avl_clk does not appear in your tech map viewer screenshot even though you preserved it in your code.

[JuanEscobedo]

Afi_clk does appear, but only on pre-synthesis view in SignalTap

The signal is missing on post-fitting view

[sstrell]

So tap it as pre-synthesis for use as the acquisition clock.

[JuanEscobedo]

What are the advantages/disadvantages of using pre synthesis vs post-fitting? Isn't the signal showing up in one but not the other a problem?

[sstrell · Accepted solution]

In this situation, it doesn't matter, it's the same signal no matter what.

Using pre-synth vs. post-fit comes more into play if you're trying to reduce recompile times (short ECO compilation with post-fit vs. full recomp with pre-synth even though in Standard edition, that isn't really a big thing either unless you are using incremental compilation).

Short answer for you: it doesn't really matter.

[JuanEscobedo]

Hello,

After changing the logic a bit and using the pre-synthesis signals to debug, I am able to get the behavior I expected:

I have attached the version of the code that worked as reference. The main difference is my state machine was waiting on a registered version of the the ready and read data valid signals (part of previous attempts at troubleshooting). Changing the valid read condition to just the original read data valid signal seems to have solved the issue. Attaching my code for future reference.