Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
15388 Discussions

MAX 10 constraint error reported to on chip flash clock.

RRomano001
New Contributor I
427 Views

Hi, I prepared a lot more of issue but I am weakened about...

This one is really out of my control:

On chip flash clock is attached to pll C0 as all peripheral are. In same pane, 1 and 5 share same clock, so why this error?

Screenshot from 2019-06-06 09:42:40.png

QSYS or Quartus? (Release 18.1 Lite Linux Hosted.)

Same behavior on Win7 version.

0 Kudos
2 Replies
KhaiChein_Y_Intel
123 Views

Hi,

 

There is one KDB about this. Can you try the workaround stated in https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base...?

 

Thanks

RRomano001
New Contributor I
123 Views

Hi YY, yes seems solve issue but not side effect. We can address this and other after fair event is coming too soon to experiment.

This issue appeared @2016, is still present.

Dear Intel remember we are not M$, we cannot sell defective product nor we can risk defect on industrial environment where mechanical part with dangerous energy get controlled by silicon.

Too few I think are interested about M$ IOT, think also what happened to smart phone market, few customer buy from a great brand it was Nokia.

My colleague use Linux or Mac as platform, few use windows.

Altera was a great company, why drive to dead end?

Regards.

 

Reply