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RRomano001
New Contributor I
353 Views

MAX 10 constraint error reported to on chip flash clock.

Hi, I prepared a lot more of issue but I am weakened about...

This one is really out of my control:

On chip flash clock is attached to pll C0 as all peripheral are. In same pane, 1 and 5 share same clock, so why this error?

Screenshot from 2019-06-06 09:42:40.png

QSYS or Quartus? (Release 18.1 Lite Linux Hosted.)

Same behavior on Win7 version.

0 Kudos
2 Replies
49 Views

Hi,

 

There is one KDB about this. Can you try the workaround stated in https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base...?

 

Thanks

RRomano001
New Contributor I
49 Views

Hi YY, yes seems solve issue but not side effect. We can address this and other after fair event is coming too soon to experiment.

This issue appeared @2016, is still present.

Dear Intel remember we are not M$, we cannot sell defective product nor we can risk defect on industrial environment where mechanical part with dangerous energy get controlled by silicon.

Too few I think are interested about M$ IOT, think also what happened to smart phone market, few customer buy from a great brand it was Nokia.

My colleague use Linux or Mac as platform, few use windows.

Altera was a great company, why drive to dead end?

Regards.

 

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