Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
14966 Discussions

Macro not being passed to Modelsim

RandyR
New Contributor I
184 Views

I am using Quartus Standard 20.1 and Modelsim Intel FPGA edition.  

My design has a header file with parameters that use `ifdef to select video parameters for different resolutions.  I also use the same macro to select the correct PLL during compilation.

The design builds properly in Quartus.  However, when I try to simulate in Modelsim, Modelsim always sees the macro as undefined.

set_global_assignment -name VERILOG_MACRO "highres=1" is in my .qsf file.  When I look at the generated .do file from NativeLink, there is no reference to the macro.

What is required to see that the macro is passed to Modelsim?

Thanks in advance, Randy

0 Kudos
1 Reply
RichardTanSY_Intel
161 Views

Hi, I found similar case to your question. Could you try the solution provided in the case?
Let me know if this helps. 

https://community.intel.com/t5/Intel-Quartus-Prime-Software/How-to-use-MACRO-on-altera-modelsim/td-p...

 

Reply