I am using Quartus Standard 20.1 and Modelsim Intel FPGA edition.
My design has a header file with parameters that use `ifdef to select video parameters for different resolutions. I also use the same macro to select the correct PLL during compilation.
The design builds properly in Quartus. However, when I try to simulate in Modelsim, Modelsim always sees the macro as undefined.
set_global_assignment -name VERILOG_MACRO "highres=1" is in my .qsf file. When I look at the generated .do file from NativeLink, there is no reference to the macro.
What is required to see that the macro is passed to Modelsim?
Thanks in advance, Randy
Hi, I found similar case to your question. Could you try the solution provided in the case?
Let me know if this helps.