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Max10 ADC simulation in QuestaSim fails to simulate output

twister1398
Beginner
460 Views

I'm trying to simulate the Max10 ADC in QuestaSim 2021.3. The ADC Core ready signal (modular_adc_0_command_ready) never goes high. I suspect that the following warning may be related to this behaviour:

Warning: (vsim-PLI-3691) Expected a system task, not a system function '<protected>'.
#    Time: 0 ps  Iteration: 0  Protected: /adc_controller_tb/adc_controller/modular_adc_0/control_internal/adc_inst/adcblock_instance/primitive_instance/inst/<protected>/<protected>/<protected> File: J:/Programme/intelFPGA_lite/18.1/quartus/eda/sim_lib/mentor/fiftyfivenm_atoms_ncrypt.v Line: 38

 

 

 

To me, it looks like QuestaSim can not read the encrytped IP file fiftyfivenm_atoms_ncrypt.v. I did compile the altera libraries for both verilog and vhdl using Quartus Prime 20.1.0 lite and used the 'Run Simulation Tool> RTL Simulation' command of quartus to set up the simulation in QuestaSim.

I attach the log files of the library compilation, as I have noticed that for the file fiftyfivenm_atoms_ncrypt.v, no top level modules are listed. Is this the expected behaviour during library compilation?

 

Any help is appreciated.

0 Kudos
1 Solution
RichardTanSY_Intel
444 Views

Hi @twister1398 

 

This is normal behavior, if you compile the fiftyfivenm_atoms_ncrypt.v standalone, you can see there are modules listed in the compiled library.  

Regarding to ready signal (modular_adc_0_command_ready) never goes high, I would suggest to review your design and testbench. 

You may checkout the User Guide below for further information:

https://www.intel.com/content/www/us/en/programmable/documentation/sam1393576011848.html#sam14561488...

 

Best Regards,
Richard Tan

p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos. 

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2 Replies
RichardTanSY_Intel
445 Views

Hi @twister1398 

 

This is normal behavior, if you compile the fiftyfivenm_atoms_ncrypt.v standalone, you can see there are modules listed in the compiled library.  

Regarding to ready signal (modular_adc_0_command_ready) never goes high, I would suggest to review your design and testbench. 

You may checkout the User Guide below for further information:

https://www.intel.com/content/www/us/en/programmable/documentation/sam1393576011848.html#sam14561488...

 

Best Regards,
Richard Tan

p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos. 

RichardTanSY_Intel
428 Views

Hi @twister1398 

 

Thank you for the best answer confirmation. I’m glad that your question has been addressed. With that, I will now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

Best Regards,
Richard Tan

p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos. 

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