Modelsim is exiting with code 211.

[Altera_Forum]

Hi, 

 every time I try to run a simulation with Modelsim I get: Modelsim is exiting with code 211. Then Modelsim closes.  Transcript says: # vsim -gui work.test_counter # Start time: 15:48:59 on Nov 17,2016# Loading work.test_counter# Loading work.counter# ** Fatal: (SIGSEGV) Bad handle or reference.# Time: 0 ns Iteration: 0 Instance: /test_counter File: C:/intelFPGA_lite/16.1/modelsim_ase/examples/tutorials/verilog/basicSimulation/tcounter.v# FATAL ERROR while loading design# Error loading design# End time: 15:48:59 on Nov 17,2016, Elapsed time: 0:00:00# Errors: 1, Warnings: 0  This happens with every file I use. This one was the example so at least that one should work.  I also tried running the simulation from Quartus.  It says something similar: # ** Fatal: (SIGSEGV) Bad handle or reference.# Time: 0 ps Iteration: 0 Instance: /half_add_vhd_vec_tst File: Waveform2.vwf.vht Line: UNKNOWN# FATAL ERROR while loading design# Error loading design Error loading design  I am using the ModelSim Starter Edition Intel FPGA 10.5b (Quartus Prime 16.1). I already tried reinstalling the program, didn't help.  Best Regards

[Altera_Forum]

SIGSEGV is a segmentation fault, - something is causing modelsim to crash. 

You may have to raise a ticket with mentor to find the problem.  Could you post the code for counter and test_counter?

[Altera_Forum]

Hi, 

 attached the two files from "C:\intelFPGA_lite\16.1\modelsim_ase\examples\tutorials\verilog\basicSimulation"

[Altera_Forum]

I highly doubt the code is causing this problem. 

For future, I highly suggest you use Verilog 2001 styles, where you can specify input/output and type on the actual ports:   module counter ( output count, input clk, reset ); function increment ( val);   It is much more readable than verilog '95.  I can only assume the crash is some setup issue. What OS are you using? How are you running the sim?

[Altera_Forum]

I'm using Win 7. 

 After opening Modelsim I press "Start Simulation", select the file and ok. That's it. I didn't change any settings.

[Altera_Forum]

Any news? 

 I've got the same issue on two machines! One running Quartus Prime Lite 16.0 and one running 16.1. No simulations work at all.  This thread seems to blame Symantec:- http://www.alteraforum.com/forum/showthread.php?t=50771&page=3  and I have Symantec on both machines. I have tried to disable it but that didn't help. I might ask IT to uninstall it for a test.  Thanks

[Altera_Forum]

I'm also using Symantec and I disabled it an excluded the intel folder but this didn't make a difference. Also the Symantec log didn't show any actions.

[Altera_Forum]

Hi, 

 Same problem appeared here this week (Modelsim 10.4b), even with one of the VHDL tutorial example design provided in Quartus 15.1. Tested on three different Win7 machines, on different designs...  Also tried to disable Symantec, no success

[Altera_Forum]

The problem comes from SEP (Symantec End point Protection), though the tools does not report any threat. 

Exception (or exclusion) policies can be created in the Symantec Endpoint Protection Manager (SEPM) under Policies - Exceptions. The fix (working for 15.1) is the following https://www.alteraforum.com/forum/attachment.php?attachmentid=13097

[beepee]

Hi, I experienced the same problem with the free SE version 10.4d, which does not need any special license.

My project is in VHDL, and this is what I had to change to get rid of the crash:

In some design unit there is an output bus using the generic e.g. BUSWIDTH

1. Entity demo is (
2. generic ( BUSWIDTH=8);
3. ..
4. );
5. port (
6. ..
7. data_out: out (BUSWIDTH-1 downto 0) := (others => '0');
8. ..
9. ); end demo;
10. architecture arch of demo is
11. ..
12. subblock_inst : subblock
13. port map (
14.   data_out <= data_out(6-1 downto 0),
15. ..
16. );
17. data_out(BUSWIDTH-1 downto 6) <= (others => '0');
18. ..
19. end arch;

Now something like this gave me the error 211 and closing after 10 seconds.

Removing the line 17 gave me an error message about unconnected IO.

Removing the default assignment in line 7 solved the problem in my case (removed ":= (others => '0')"

So it looks like the split bus assignments together with default assignments is problematic