Multi source?

[Altera_Forum]

Hello. 

 I am trying to make a mac component. Everything is fine, until I put acc (my accumulator) receiving the output value.  The strange thing is that Quartus sythetize it, but Modelsim acuse a multi-source and responde with X in output value. Do you guys have any ideas?  Here is the code: library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;   ENTITY main IS  generic (  size : integer := 4;  port (  clk : in std_logic;  rst : in std_logic;  a_i : in std_logic_vector(size-1 downto 0);  b_i : in std_logic_vector(size-1 downto 0);  out_o : out std_logic_vector(2*size-1 downto 0)  ); END main;     ARCHITECTURE bhv OF main IS  COMPONENT mac  generic (  width : integer);  port (  clk : in std_logic;  rst : in std_logic;  a_i : in std_logic_vector(width-1 downto 0);  b_i : in std_logic_vector(width-1 downto 0);  acc : in std_logic_vector(2*width-1 downto 0);  out_sig : out std_logic_vector(2*width-1 downto 0)  );  END COMPONENT;    signal acc, out_sig, out_acc : std_logic_vector(2*size-1 downto 0) := (others => '0');     BEGIN    mac1: mac GENERIC MAP (size) PORT MAP (clk, rst, a_i, b_i, acc, out_sig);    reg_out : process(clk, rst)  begin  if rst = '1' then  out_o <= (others => '0');  elsif clk'event and clk = '1' then  out_o <= out_sig;  end if;  end process;     reg_acc : process(clk, rst)  begin  if rst = '1' then  acc <= (others => '0');  elsif clk'event and clk = '1' then  acc <= out_sig;  end if;  end process;      END bhv;

[Altera_Forum]

Try to replace this line 

  mac1 : mac GENERIC MAP (size) PORT MAP (clk, rst, a_i, b_i, acc, out_sig);  With this   mac1 : mac GENERIC MAP ( width => size ) PORT MAP ( clk => clk, rst => rst, a_i => a_i, b_i => b_i, acc => acc, out_sig => out_sig );  If the entity of "mac" has a different signal order then your component declaration you avoid problems with explicitly mapping each signal this way.

[Altera_Forum]

https://www.alteraforum.com/forum/attachment.php?attachmentid=6542  

I attached the response. At a certain moment, value is X.  Also, the result is stable, it isnt summing as required.

[Altera_Forum]

I think you should set your reset signal to a defined state in your testbench, currently it is undefined.

[Altera_Forum]

Did it, but the problem continues.

[Altera_Forum]

In the signal declaration you assign (OTHERS => '0') to "out_sig" try to replace your signal declaration: 

  SIGNAL acc, out_sig, out_acc : std_logic_vector(2*size-1 DOWNTO 0) := (OTHERS => '0');   with this code:   SIGNAL acc : std_logic_vector(2*size-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL out_acc : std_logic_vector(2*size-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL out_sig : std_logic_vector(2*size-1 DOWNTO 0);

[Altera_Forum]

Nothing =/

[Altera_Forum]

Currently I only can make an educated guess on behalf of your error description what may be wrong with your VHDL code. 

The best way would be if I can replicate the problem on my side, but for this I would need the code your "mac" component and your testbench.

[Altera_Forum]

If you wanna it, i can send you by email. Should I?

[Altera_Forum]

Send it. Thanks schmalisch