Multiplication VHDL

[Altera_Forum]

Hi, i have problems with my vhdl code.  

 can you help me plz   This is the code:  library ieee;use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_arith.all ; entity correla is port ( clk : in std_logic ; rst : in std_logic ; data: in std_logic_vector(11 downto 0) ; code: in std_logic_vector(15 downto 0 ) ; Q : out std_logic_vector(17 downto 0) ) ; end entity ; architecture arch of correla is type RAM is array (0 to 3) of integer range -8 to 7 ; signal CD : RAM; signal temp :integer range 0 to 15; signal i :integer range 0 to 3 ; signal sum :integer range 0 to 16 ; signal AB :integer range 0 to 17 ; begin CD(0)<=to_integer(code(15 downto 12)); CD(1)<=to_integer(code(11 downto 8)) ; CD(2)<=to_integer(code(7 downto 4 )) ; CD(3)<=to_integer(code(3 downto 0)) ; étalement:process(clk,rst) begin if(rst='1') then Q<=(others=>'0'); i<= 0 ; temp<=0; AB<=0; else if(clk'event and clk ='1') then sum<=0; temp<=to_integer(data(i)*code(i)) ; i<=i+1 ; sum<=sum(i) +(temp(i)+temp(i+1)) ; end if ; end if ; AB<=sum ; Q<=std_logic_vector(AB) ; end process ; end architecture ;    

[Altera_Forum]

What is the problem?  

If you ask a more concrete question we can help you out. This also looks quite similar to http://www.alteraforum.com/forum/showthread.php?t=45040 Attempt something yourself first, if something is wrong, try to think why, if you cannot answer why, then as here.

[Altera_Forum]

Hi, 

I am not sure but you should remove the line "use IEEE.std_logic_arith.all;", It may redefine operators.  Avoid éèçàù... : c'est trop français pour du VHDL ;-)  Be aware that integer = 32 bits in VHDL  VHDL needs a very strict description : Your 'i' is integer range 0 to 3. OK somewhere you have   i<=i+1 ; What happens if i = 3 ? Not sure that i returns to 0 !  if i <= 3 then i <= i + 1; else i <= 0; end if;   What is the value of "sum" when rst = '1' ? You must initialize ALL signals to avoid spending hours to debug. ... ...  BUT your VHDL does NOT describe your schéma !!!  For a beginner, If your design have always 4 mult and 3 add, I advise you to draw your schema completely : all signals are named.  Write your VHDL element per element :  mult1 : ... <= ... * ... ; mult2 : ... <= ... * ...; ... add1 : ... <= ... + ....; -- be careful that with IEEE.numeric_std : 16bits + 16bits => 16bits, not 17bits !!  And add a D flip flop at the end, to stay synchronous. To create a D flip flop, it is just a  process(rst,clk) begin if rst = '1' then Q <= (others => '0'); elsif rising_edge(clk) then Q <= AB; -- AB is the result of the "logique combinatoire" which may glitchs end if; end process;   later, you can make this design more generic as you badly tried. use generic, generate...  In a near future, if fmax is not satisfied, you can pipeline : insert D flip flop between mult and add, but it increase latency.  Welcome to the dark side of VHDL ;-) golden rule[/orange] : vhdl is a description language, NOT a program.

[Altera_Forum]

In the fact , what is the differebce between : std_logic_vector(3 downto 0) et integer range 0 to 3 ???! 

 thank you !

[Altera_Forum]

an integer is in hardware no different than a std_logic_vector(I think), but an integer with range 0 to 3 is different than a vector of 3 downto 0.  

"00" = 0 "01" = 1 "10" = 2 "11" = 3 so 2 bits for the integer, and a vector 3 downto 0 has 4 bits: 3,2,1,0.  But I suggest reading books about VHDL if your questions are at this level.

[Altera_Forum]

--- Quote Start ---  an integer is in hardware no different than a std_logic_vector(I think), but an integer with range 0 to 3 is different than a vector of 3 downto 0.  "00" = 0 "01" = 1 "10" = 2 "11" = 3 so 2 bits for the integer, and a vector 3 downto 0 has 4 bits: 3,2,1,0.  But I suggest reading books about VHDL if your questions are at this level.  --- Quote End ---     Thank you for your reponse

[Altera_Forum]

--- Quote Start ---  In the fact , what is the differebce between : std_logic_vector(3 downto 0) et integer range 0 to 3 ???!  thank you !  --- Quote End ---    A std_logic_vector is just a collection of bits, it was not intended to be used for numbers. An integer is a number that has no bits until synthesised. So you need to contrain it to bit appropriate bit widths. Use whatever is appropriate in your code. Read up on VHDL and it's strong type system - dont fight against it.

[Altera_Forum]

Hi ! 

 plz can you help me to correct :  library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity correla is  port (  clk : in std_logic ;  rst : in std_logic ;  data: in std_logic_vector(11 downto 0) ;  code: in std_logic_vector(15 downto 0 ) ;    Q :out std_logic_vector(17 downto 0) ) ; end entity ;  architecture arch of correla is      type RAM is array (0 to 3) of std_logic_vector(-8 to 7) ;  signal CD : RAM;  signal temp :integer range 0 to 15;    signal idata :std_logic_vector(11 downto 0) ;  signal sum :integer range 0 to 16 ;  signal AB :integer range 0 to 17 ;   begin    F:for j in 0 to 3 generate   CD(j)<=to_integer(signed(code((4*j+3) downto (4*j))));    end generate F ;       étalement:process(clk,rst)    begin   if(rst='1') then   Q <=(others=>'0');    temp<=0;  AB <=0;    else   if(clk'event and clk ='1') then   sum<=0;    for i in 0 to 3 loop   temp(i)<=to_integer(data(i)*CD(i)) ;  i<= i+1 ;   sum(i)<=sum(i) +temp(i) ;    if(i=3) then   idata<=data;  end if;  end loop ;    AB<=sum ;  Q<=std_logic_vector(AB) ;        end if ;  end if ;         end process ;  end architecture ;   erreur : Error (10511): VHDL Qualified Expression error at correla.vhd(29): TO_INTEGER type specified in Qualified Expression must match std_logic_vector type that is implied for expression by context  Thanks a lot

[Altera_Forum]

and now : 

 code :  library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity correla is  port (  clk : in std_logic ;  rst : in std_logic ;  data: in std_logic_vector(11 downto 0) ;  code: in std_logic_vector(15 downto 0 ) ;    Q :out std_logic_vector(17 downto 0) ) ; end entity ;  architecture arch of correla is      type RAM is array (0 to 3) of std_logic_vector(-8 to 7) ;  signal CD : RAM;  signal temp :integer range 0 to 15;    signal idata :std_logic_vector(11 downto 0) ;  signal sum :integer range 0 to 16 ;  signal AB :integer range 0 to 17 ;   begin    CD(0)<=(code(15 downto 12));  CD(1)<=(code(11 downto 8)) ;  CD(2)<=(code(7 downto 4 ));  CD(3)<=(code(3 downto 0));    étalement:process(clk,rst)    begin   if(rst='1') then   Q <=(others=>'0');    temp<=0;  AB <=0;    else   if(clk'event and clk ='1') then   sum<=0;    for i in 0 to 3 loop   temp(i)<=to_integer(data(i)*CD(i)) ;  sum(i)<=sum(i) +temp(i) ;  i<= i+1 ;  if(i=3) then   idata<=data;  end if;  end loop ;    AB<=sum ;  Q<=std_logic_vector(AB) ;        end if ;  end if ;         end process ;  end architecture ;   ?! thank you in advance for your answer

[Altera_Forum]

wow, many problems. 

1. Std_logic_vector cannot have -ve indeces. 2. Even with correct indeces lengths, CD(0) would have 16 bits, not 4, so CD(i) <= code(15 downto 12); would have an error from incorrect sizes. 2. Sum and temp are integers, hence you cannot index to individual bits. 3. data(i) is a single std_logic. You cannot do std_logic * std_logic_vector. Hence, there is no possible result, and to_integer is not appropriate.  4. i <= i + 1; is illegal as i is a constant, not a signal. 5. you cannot cast in integer to a std_logic_vector directly, you need to go via the signed or unsigned type.  Q <= std_logic_vector( to_unsigned(AB, Q'length));   I highly suggest you go back to your VHDL manual and start reading it.

[Altera_Forum]

like this : 

 library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;   entity correla is  port (  clk : in std_logic ;  rst : in std_logic ;  data: in std_logic_vector(11 downto 0) ;     code: in std_logic_vector(15 downto 0 ) ;    Q :out std_logic_vector(17 downto 0) ) ; end entity ;  architecture arch of correla is   type RAM is array (0 to 3) of std_logic_vector(3 downto 0) ;    type ram16 is array (0 to 3) of signed(15 downto 0) ;   signal CD : RAM;  signal temp: ram16;         signal sum :signed (16 downto 0) ;  signal AB :signed (17 downto 0) ;   begin    CD(0) <= code(15 downto 12);  CD(1) <= code(11 downto 8);  CD(2) <= code(7 downto 4);  CD(3) <= code(3 downto 0);   étalement:process(clk,rst)    begin   if(rst='1') then   Q <=(others=>'0');    temp(0)<=x"0000";  temp(1)<=x"0000";  temp(2)<=x"0000";  temp(3)<=x"0000";      else   if(clk'event and clk ='1') then         for i in 0 to 3 loop   temp(i) <= signed(data)*signed(CD(i));  end loop ;    sum(0)<= temp(0)+temp(1) ;  sum(1)<= temp(2)+temp(3) ;    AB<=sum(0)+sum(1) ;    Q<=std_logic_vector(AB) ;   --          end if ;  end if ;         end process ;  end architecture ;   error : Error (10327): VHDL error at correla.vhd(60): can't determine definition of operator ""+"" -- found 0 possible definitions   60: sum(0)<= temp(0)+temp(1) ;  can you help me

[Altera_Forum]

sum(0) is a single bit, not an array.

[Altera_Forum]

yeah !  

 like this :  library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;   entity correla is  port (  clk : in std_logic ;  rst : in std_logic ;  data: in std_logic_vector(11 downto 0) ;     code: in std_logic_vector(15 downto 0 ) ;    Q :out std_logic_vector(17 downto 0) ) ; end entity ;  architecture arch of correla is   type RAM is array (0 to 3) of std_logic_vector(3 downto 0) ;    type ram16 is array (0 to 3) of signed(15 downto 0) ;  type Rom is array (0 to 3) of signed(16 downto 0) ;   signal CD : RAM;  signal temp: ram16;  signal sum :Rom ;           signal AB :signed (17 downto 0) ;   begin    CD(0) <= code(15 downto 12);  CD(1) <= code(11 downto 8);  CD(2) <= code(7 downto 4);  CD(3) <= code(3 downto 0);   étalement:process(clk,rst)    begin   if(rst='1') then   Q <=(others=>'0');    temp(0)<=x"0000";  temp(1)<=x"0000";  temp(2)<=x"0000";  temp(3)<=x"0000";  sum(0)<=x"00000";  sum(1)<=x"00000";      else   if(clk'event and clk ='1') then         for i in 0 to 3 loop   temp(i) <= signed(data)*signed(CD(i));  end loop ;    sum(0)<= temp(0)+temp(1) ;  sum(1)<= temp(2)+temp(3) ;    AB<=sum(0)+sum(1) ;    Q<=std_logic_vector(AB) ;   --          end if ;  end if ;         end process ;  end architecture ;  error : Error (10324): VHDL Expression error at correla.vhd(55): expression ""0000000000000000"" has 16 elements ; expected 17 elements.  55 : sum(0)<=x"0000";  can you help me !!

[Altera_Forum]

like this : 

  library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;   entity correla is  port (  clk : in std_logic ;  rst : in std_logic ;  data: in std_logic_vector(11 downto 0) ;     code: in std_logic_vector(15 downto 0 ) ;    Q :out std_logic_vector(17 downto 0) ) ; end entity ;  architecture arch of correla is   type RAM is array (0 to 3) of std_logic_vector(3 downto 0) ;    type ram16 is array (0 to 3) of signed(15 downto 0) ;  type Rom is array (0 to 3) of signed(16 downto 0) ;   signal CD : RAM;  signal temp: ram16;  signal sum :Rom ;           signal AB :signed (17 downto 0) ;   begin    CD(0) <= code(15 downto 12);  CD(1) <= code(11 downto 8);  CD(2) <= code(7 downto 4);  CD(3) <= code(3 downto 0);   etalement:process(clk,rst)    begin   if(rst='1') then   Q <=(others=>'0');    temp(0)<=x"0000";  temp(1)<=x"0000";  temp(2)<=x"0000";  temp(3)<=x"0000";  sum(0)<="00000000000000000";  sum(1)<="00000000000000000";      else   if(clk'event and clk ='1') then         for i in 0 to 3 loop   temp(i) <= signed(data)*signed(CD(i));  end loop ;    sum(0)<= temp(0)+temp(1) ;  sum(1)<= temp(2)+temp(3) ;    AB<=sum(0)+sum(1) ;    Q<=std_logic_vector(AB) ;   --          end if ;  end if ;         end process ;  end architecture ;  error : Error (10344): : expression has 16 elements, but must have 17 elements   sum(0)<= temp(0)+temp(1) ;  thanks a lot

[Altera_Forum]

The error messages are usually quite helpful 

The answer is that the expression has 16 elements, but sum has 17

[Altera_Forum]

Ok Thank you !