I am trying to import my custom RTL code and create a new component for integrating into the existing system on Platform Designer. I am getting the below error message when i do "Analyze SynthesisFiles" step while importing the Files (tab):
Error: Peak virtual memory: 4763 megabytes
Error: Processing ended: Mon Dec 17 11:15:39 2018
Error: Elapsed time: 00:00:11
Error: Total CPU time (on all processors): 00:00:01
There is no additional information as to where the error exists or how to fix. So i even tried to have only the port list in the RTL file to create a new component (by commenting off the rest of the logic in the Verilog module file). Even with this modelsim compile clean minimal RTL above error is seen.
I even tried to run the quartus_map, to see if any additional error messages are displayed. But here also there is no additional information. (See attached logs)
Could you please recommend how to workaround this problem? How to see any additional
All you have is a port list, so you've essentially created just a black box. Is that your intent?
I'm not sure why you're having an issue. Things I'd try: getting rid of the comments, removing the spaces within the square brackets ([ 3:0] for example.
These error messages could displayed because your design is using too many logic resources that is actually too large to fit in your device.
What device you're using?