New to VHDL. . . and this error is adding years to my life!

[Altera_Forum]

Hello all. New to this forum, and will probably be more active since this stuff is not innate to me. Anyways, I am trying to make a stopwatch that has the following properties: 

 1. When you press KEY3, it will start 2. When you press KEY3 a second time, it will pause 3. When you press KEY3 a third time, it will reset and go back to step 1. 4. Any time pressing KEY0 will reset and stop the counter.  I keep getting an error that I do not know how to resolve:  Error (10028): Can't resolve multiple constant drivers for net "clock_1k" at lab2_4_new2.vhd(58)  I'm almost positive that it is something simple, but im getting frustrated with all this, so here I am!   Thanks in advance!  -Ron   LIBRARY IEEE; USE IEEE.std_logic_1164.all; USE IEEE.numeric_std.all; ENTITY lab2_4_new2 IS PORT( CLOCK_50: IN std_logic; SW : IN std_logic_vector(3 DOWNTO 0); KEY: IN std_logic_vector(3 downto 0); HEX0, HEX1, HEX2, HEX3: OUT std_logic_vector(6 DOWNTO 0) ); END lab2_4_new2; ARCHITECTURE Counter of lab2_4_new2 IS signal enable : std_logic; --filtered key(3) pushbutton signal signal clock_1k : std_logic; --internally generated 10KHz clock signal n0, n1, n2, n3: unsigned(3 downto 0); --five decimal digits signal buttonpress : std_logic; signal reset: std_logic; type state_type is (wait_for_press, wait_for_release1, Run, wait_for_release2, pause, wait_for_release3); signal state: state_type; BEGIN --------------------------------------------------------- --The four decimal digits are declared as "unsigned" type --so the arithmetic operations can be easily described. --However, they must be converted to std_logic_vector --type before sending to "sevenseg" for further --conversion to 7-segment display patterns. --------------------------------------------------------- display0: entity work.sevenseg port map (std_logic_vector(n0), HEX0); display1: entity work.sevenseg port map (std_logic_vector(n1), HEX1); display2: entity work.sevenseg port map (std_logic_vector(n2), HEX2); display3: entity work.sevenseg port map (std_logic_vector(n3), HEX3); -------------------------------------------------------- --The debounced circuit is used to "filtered" out --the bounces in the pushbutton signal -------------------------------------------------------- pushbutton_debounce : entity work.debounce generic map( CYCLES => 16 ) port map( pin => key(3), output => buttonpress, clock => clock_50 ); -------------------------------------------------------- --Following circuit generates a 10KHz clock from the --input 50MHz. The signal clock_10k is initialized to --'0' and is flipped each time loopcount reaches 2500. --Thus, the cycle time of clock_10k is decided by --2*2500=5000; and thus clock_10k frequency is --50MHz/5000=10KHz. -------------------------------------------------------- Clock_Gen_100Hz: PROCESS (clock_50, KEY(0)) variable loopcount : integer range 0 to 2500000; BEGIN IF(KEY(0) = '0') THEN --KEY0 is the asynchronous reset button clock_1k <= '0'; loopcount := 0; ELSIF(clock_50'event AND clock_50 = '1') THEN if(loopcount = 2499999) then loopcount := 0; clock_1k <= not clock_1k; --flip clock_10K else loopcount := loopcount + 1; end if; END IF; END PROCESS; -------------------------------------------------------- --Following circuit runs on the 1KHz clock and thus --the fourth digit (n3) is updated once every second --The filtered key(3), "pause", is used to "enable" --this running counter. Note that key(3) is negative --logic meaning that when push key(3)='0' and when --release key(3)='1'. Thus the following design will --allow the counter to run only when key(3) is pressed. -------------------------------------------------------- Running_counter: PROCESS(clock_1k, key(0)) BEGIN IF(key(0) = '0') THEN --KEY0 is the asynchronous reset button n0 <= "0000"; -- reset the decimal number to "00000" n1 <= "0000"; n2 <= "0000"; n3 <= "0000"; ELSIF(clock_1k'event AND clock_1k = '1') THEN if( enable = '1') then if(n0="1001") then --when n0=9, instead of inc n0 reset it to 0 n0 <= "0000"; if(n1="1001") then --when n1=9, instead of inc n1 reset it to 0 n1 <= "0000"; if(n2="1001") then n2 <= "0000"; if(n3="1001") then n3 <= "0000"; else n3 <= n3 + 1; end if; else n2 <= n2 + 1; end if; else n1 <= n1 + 1; --when n1 /= 9, inc n1 end if; else n0 <= n0 + 1; --when n0 /= 9, inc n0 end if; end if; END IF; END PROCESS; FSM: Process(clock_1k, buttonpress, reset) BEGIN If (reset='1') then clock_1k <= '0'; state <= wait_for_press; -- IF(key(0) = '0') THEN -- reset <= '1'; -- enable <= '0'; -- state <= wait_for_press; elsif (clock_1k'event and clock_1k='1') then case state is when wait_for_press => if (buttonpress='0') then reset <= '0'; enable <='1'; state <= wait_for_release1; end if; when wait_for_release1 => if (buttonpress='1') then state <= Run; end if; when Run => if (buttonpress='0') then enable <='0'; state <= wait_for_release2; end if; when wait_for_release2 => if (buttonpress='1') then state <= pause; end if; when pause => if (buttonpress='0') then reset <='1'; state <= wait_for_release3; end if; when wait_for_release3 => if (buttonpress='1') then state <= wait_for_press; end if; when others => state <= wait_for_press; end case; end if; end process; end architecture;

[Altera_Forum]

You are assigning a value to clock_1k in more than one process. 

 FSM: Process(clock_1k, buttonpress, reset)   Clock_Gen_100Hz: PROCESS (clock_50, KEY(0))    These two processes both modify the clock_1k signal. That is incorrect behavior. Get rid of it in the FSM process and the error will go away.

[Altera_Forum]

OK, I see what you are saying. Then I am unsure how I am to get the counter to "reset" during the FSM state "pause". I think the problem is that I am not really defining the function of "reset", and I dont quite see how to do this without making 2 processes be able to set the counter generated from clock1k to '0' 

 EDIT: Nevermind, I just figured it out! Thank you so much for your help!

[Altera_Forum]

Hi, In your Clock_Gen_100Hz process you have used KEY(0) as asyn reset.Instead of that give high priority to reset and within clcok give priority to key(0).I have modified as  

  IF(reset='1') THEN --KEY0 is the asynchronous reset button   clock_1k <= '0';   loopcount := 0;   ELSIF(clock_50'event AND clock_50 = '1') THEN   IF(KEY(0) = '0') THEN  clock_1k <= '0';   loopcount := 0;   elsif(loopcount = 2499999) then   loopcount := 0;   clock_1k <= not clock_1k; --flip clock_10K     else   loopcount := loopcount + 1;   end if;   END IF;   And Dont forget remove assignment of clock_1k <= '0'; from FSM process.

[Altera_Forum]

--- Quote Start ---  Hi, In your Clock_Gen_100Hz process you have used KEY(0) as asyn reset.Instead of that give high priority to reset and within clcok give priority to key(0).  --- Quote End ---    There is nothing wrong with this for altera chips, as long as key is synchronised. There are no sync resets on altera registers, only async ones. Sync resets have to be emulated with a mux. So using an async reset from a synchronous source is actually the best way to reset registers because you use the least logic.

[Altera_Forum]

--- Quote Start ---  There is nothing wrong with this for altera chips, as long as key is synchronised. There are no sync resets on altera registers, only async ones. Sync resets have to be emulated with a mux. So using an async reset from a synchronous source is actually the best way to reset registers because you use the least logic.  --- Quote End ---   Yeah Tricky, I have accept that. but the concern is deftonesrc reset the clock_1k signal in two process. One is with respect to reset signal in one process, and with respect to KEY(0) signal. So I just combined both logics in one process. Otherwise I dont have any concern about async reset.