Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
15385 Discussions

PLL instantiation .clk#_phase_shift() string problem.

BrianHG
New Contributor I
127 Views

Hello, I am trying to write a SystemVerilog PLL instantiation with 3 outputs at a parameter select-able phase.  This is the 'just' of my code.

 

-----------------------------------------------------------

parameter string FPGA_VENDOR = "Altera",
parameter int CLK_KHZ_IN = 50000,
parameter int CLK_IN_MULT = 10,
parameter int CLK_IN_DIV = 1,

parameter string INTERFACE_SPEED = "Half",

parameter bit [8:0] DDR3_WDQ_PHASE = 90,
parameter bit [8:0] DDR3_RDQ_PHASE = 45

.......

localparam int DDR3_WDQ_PHASE_ps = ((1000000 / ( CLK_KHZ_IN/1000 * CLK_IN_MULT / CLK_IN_DIV )) * DDR3_WDQ_PHASE / 360) -1 ;
localparam int DDR3_RDQ_PHASE_ps = ((1000000 / ( CLK_KHZ_IN/1000 * CLK_IN_MULT / CLK_IN_DIV )) * DDR3_RDQ_PHASE / 360) -1 ;

 

.......

// **********************************************************
// *** Begin Initiate Altera PLL for clk_pixel generation ***
// **********************************************************

altpll HPLL1 ( .inclk ({1'b0, CLK_IN}), .clk (PLL1_clk_out),
.activeclock (), .areset (RST_PLL), .clkbad (), .clkena ({6{1'b1}}), .clkloss (),
.clkswitch (1'b0), .configupdate (1'b0), .enable0 (), .enable1 (), .extclk (),
.extclkena ({4{1'b1}}), .fbin (1'b1), .fbmimicbidir (), .fbout (), .fref (),
.icdrclk (), .locked (PLL_LOCKED), .pfdena (1'b1), .phasedone (), .phasestep (1'b1),
.phaseupdown (1'b1), .pllena (1'b1), .scanaclr (1'b0), .scanclk (1'b0), .scanclkena (1'b1),
.scandata (1'b0), .scandataout (), .scandone (), .scanread (1'b0), .scanwrite (1'b0),
.sclkout0 (), .sclkout1 (), .vcooverrange (), .vcounderrange (), .phasecounterselect ({4{1'b1}}));
defparam
HPLL1.bandwidth_type = "AUTO", HPLL1.inclk0_input_frequency = PLL1_inps, HPLL1.compensate_clock = "CLK0", HPLL1.lpm_hint = "CBX_MODULE_PREFIX=HDMI_PLL",
HPLL1.clk0_divide_by = CLK_IN_DIV, HPLL1.clk0_duty_cycle = 50, HPLL1.clk0_multiply_by = CLK_IN_MULT, HPLL1.clk0_phase_shift = "0",
HPLL1.clk1_divide_by = CLK_IN_DIV, HPLL1.clk1_duty_cycle = 50, HPLL1.clk1_multiply_by = CLK_IN_MULT, HPLL1.clk1_phase_shift = DDR3_WDQ_PHASE_ps,
HPLL1.clk2_divide_by = CLK_IN_DIV, HPLL1.clk2_duty_cycle = 50, HPLL1.clk2_multiply_by = CLK_IN_MULT, HPLL1.clk2_phase_shift = DDR3_RDQ_PHASE_ps,
HPLL1.clk3_divide_by = CMD_CLK_DIV, HPLL1.clk3_duty_cycle = 50, HPLL1.clk3_multiply_by = CLK_IN_MULT, HPLL1.clk3_phase_shift = "0",

HPLL1.lpm_type = "altpll", HPLL1.operation_mode = "NORMAL", HPLL1.pll_type = "AUTO", HPLL1.port_activeclock = "PORT_UNUSED",
HPLL1.port_areset = "PORT_USED", HPLL1.port_clkbad0 = "PORT_UNUSED", HPLL1.port_clkbad1 = "PORT_UNUSED", HPLL1.port_clkloss = "PORT_UNUSED",
HPLL1.port_clkswitch = "PORT_UNUSED", HPLL1.port_configupdate = "PORT_UNUSED", HPLL1.port_fbin = "PORT_UNUSED", HPLL1.port_inclk0 = "PORT_USED",
HPLL1.port_inclk1 = "PORT_UNUSED", HPLL1.port_locked = "PORT_USED", HPLL1.port_pfdena = "PORT_UNUSED", HPLL1.port_phasecounterselect = "PORT_UNUSED",
HPLL1.port_phasedone = "PORT_UNUSED", HPLL1.port_phasestep = "PORT_UNUSED", HPLL1.port_phaseupdown = "PORT_UNUSED", HPLL1.port_pllena = "PORT_UNUSED",
HPLL1.port_scanaclr = "PORT_UNUSED", HPLL1.port_scanclk = "PORT_UNUSED", HPLL1.port_scanclkena = "PORT_UNUSED", HPLL1.port_scandata = "PORT_UNUSED",
HPLL1.port_scandataout = "PORT_UNUSED", HPLL1.port_scandone = "PORT_UNUSED", HPLL1.port_scanread = "PORT_UNUSED", HPLL1.port_scanwrite = "PORT_UNUSED",
HPLL1.port_clk0 = "PORT_USED", HPLL1.port_clk1 = "PORT_USED", HPLL1.port_clk2 = "PORT_USED", HPLL1.port_clk3 = "PORT_USED",
HPLL1.port_clk4 = "PORT_UNUSED", HPLL1.port_clk5 = "PORT_UNUSED", HPLL1.port_clkena0 = "PORT_UNUSED", HPLL1.port_clkena1 = "PORT_UNUSED",
HPLL1.port_clkena2 = "PORT_UNUSED", HPLL1.port_clkena3 = "PORT_UNUSED", HPLL1.port_clkena4 = "PORT_UNUSED", HPLL1.port_clkena5 = "PORT_UNUSED",
HPLL1.port_extclk0 = "PORT_UNUSED", HPLL1.port_extclk1 = "PORT_UNUSED", HPLL1.port_extclk2 = "PORT_UNUSED", HPLL1.port_extclk3 = "PORT_UNUSED",
HPLL1.width_clock = 5, HPLL1.intended_device_family = "Cyclone V";
// *******************************
// *** End Initiate Altera PLL ***
// *******************************

-------------------------------------------------------------------

The problem is that my calculated 'DDR3_WDQ_PHASE_ps' & 'DDR3_RDQ_PHASE_ps' are integers, but for some reason, the 'altpll' only accepts a string.

How do I convert the computed integer parameter into a string parameter so it will be accepted by the 'altpll' ?

 

0 Kudos
0 Replies
Reply